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ADV7174BCP-REEL View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7174BCP-REEL Chip Scale PAL/NTSC Video Encoder with Advanced Power Management ADI
Analog Devices ADI
ADV7174BCP-REEL Datasheet PDF : 52 Pages
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ADV7174/ADV7179
TELETEXT REQUEST CONTROL REGISTER (TC07)
Bits:
Address:
TC07–TC00
SR4–SR0 = 19H
Teletext control register is an 8-bit-wide register (see Figure 50).
Table 17. Teletext Request Control Register
Bit Name
Bit No.
TTXREQ Rising Edge Control
TC07–TC04
TTXREQ Falling Edge Control
TC03–TC00
Description
These bits control the position of the rising edge of TTXREQ. It can be
programmed from 0 CLOCK cycles to a maximum of 15 CLOCK cycles (see
Figure 50).
These bits control the position of the falling edge of TTXREQ. It can be
programmed from zero CLOCK cycles to a max of 15 CLOCK cycles. This controls
the active window for Teletext data. Increasing this value reduces the amount of
Teletext bits below the default of 360. If Bits TC03–TC00 are 00H when Bits TC07–
TC04 are changed, the falling edge of TTXREQ tracks that of the rising edge, i.e.,
the time between the falling and rising edge remains constant (see Figure 49).
CGMS_WSS REGISTER 0 (C/W0)
Bits:
Address:
C/W07–C/W00
SR4–SR0 = 16H
CGMS_WSS Register 0 is an 8-bit-wide register. Figure 51 shows the operations under the control of this register.
TC07
TC06
TC05
TC04
TC03
TC02
TC01
TC00
TTXREQ RISING EDGE CONTROL
TC07 TC06 TC05 TC04
0
0
0
0
0
0
0
1
"
"
"
"
1
1
1
0
1
1
1
1
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
TTXREQ FALLING EDGE CONTROL
TC03 TC02 TC01 TC00
0
0
0
0
0
0
0
1
"
"
"
"
1
1
1
0
1
1
1
1
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
Figure 50. Teletext Control Register
C/W07
C/W06
C/W05
C/W04
C/W03
C/W02
C/W01
C/W00
WIDE SCREEN
SIGNAL CONTROL
C/W07
0 DISABLE
1 ENABLE
CGMS ODD FIELD
CONTROL
C/W05
0 DISABLE
1 ENABLE
CGMS EVEN FIELD
CONTROL
C/W06
0 DISABLE
1 ENABLE
CGMS CRC CHECK
CONTROL
C/W04
0 DISABLE
1 ENABLE
C/W03 – C/W00
CGMS DATA BITS
Table 18. C/W0 Bit Description
Bit Name
Bit No.
CGMS Data Bits
C/W03–C/W00
CGMS CRC Check Control C/W04
CGMS Odd Field Control
CGMS Even Field Control
WSS Control
C/W05
C/W06
C/W07
Figure 51. CGMS_WSS Register 0
Description
These four data bits are the final four bits of the CGMS data output stream. Note it is
CGMS data ONLY in these bit positions, i.e., WSS data does not share this location.
When this bit is enabled (1), the last six bits of the CGMS data, i.e., the CRC check
sequence, are calculated internally by the ADV7174/ADV7179. If this bit is disabled (0), the
CRC values in the register are output to the CGMS data stream.
When this bit is set (1), CGMS is enabled for odd fields. Note this is only valid in NTSC mode.
When this bit is set (1), CGMS is enabled for even fields. Note this is only valid in NTSC mode.
When this bit is set (1), wide screen signaling is enabled. Note this is only valid in PAL mode.
Rev. B | Page 37 of 52
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