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ADV7174BCP-REEL View Datasheet(PDF) - Analog Devices

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ADV7174BCP-REEL Datasheet PDF : 52 Pages
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ADV7174/ADV7179
TIMING MODE REGISTER 1 (TR1)
Bits:
Address:
TR17–TR10
SR4–SR0 = 08H
Timing Register 1 is an 8-bit-wide register. Figure 44 shows the various operations under the control of Timing Register 1. This register
can be read from as well written to. This register can be used to adjust the width and position of the master mode timing signals.
TR17
TR16
TR15
TR14
TR13
TR12
TR11
TR10
HSYNC TO PIXEL
DATA ADJUST
TR17 TR16
00
01
10
11
0 × TPCLK
1 × TPCLK
2 × TPCLK
3 × TPCLK
HSYNC TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
TR15 TR14
x0
x1
TC
TB
TB + 32μs
VSYNC WIDTH
(MODE 2 ONLY)
TR15 TR14
0
0
1 × TPCLK
0
1
4 × TPCLK
1
0 16 × TPCLK
1
1 128 × TPCLK
TIMING MODE 1 (MASTER/PAL)
LINE 1
HSYNC
TA
TB
FIELD/VSYNC
HSYNC TO
FIELD/VSYNC DELAY
TR13 TR12
00
01
10
11
TB
0 × TPCLK
4 × TPCLK
8 × TPCLK
16 × TPCLK
HSYNC WIDTH
TR11 TR10
TA
0
0
1 × TPCLK
0
1
4 × TPCLK
1
0
16 × TPCLK
1
1
128 × TPCLK
LINE 313
TC
LINE 314
Figure 44. Timing Register 1
Table 16. TR1 Bit Description
Bit Name
Bit No.
HSYNC Width
TR11–TR10
HSYNC to FIELD/VSYNC
Delay
TR13–TR12
HSYNC to FIELD Rising
Edge Delay
TR15–TR14
VSYNC Width
TR15–TR14
HSYNC to Pixel Data Adjust TR17–TR16
Description
These bits adjust the HSYNC pulse width.
These bits adjust the position of the HSYNC output relative to the FIELD/VSYNC output.
When the ADV7174/ADV7179 is in Timing Mode 1, these bits adjust the position of the HSYNC
output relative to the FIELD output rising edge.
When the ADV7174/ADV7179 is configured in Timing Mode 2, these bits adjust the VSYNC
pulse width.
This enables the HSYNC to be adjusted with respect to the pixel data. This allows the Cr and Cb
components to be swapped. This adjustment is available in both master and slave timing modes.
Rev. B | Page 34 of 52
 

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