|ADV7174KCPZ||Chip Scale PAL/NTSC Video Encoder with Advanced Power Management|
|ADV7174KCPZ Datasheet PDF : 52 Pages |
TIMING MODE REGISTER 0 (TR0)
SR4–SR0 = 07H
Figure 43 shows the various operations under the control of Timing Register 0. This register can be read from as well as written to.
0 SLAVE TIMING
1 MASTER TIMING
0 8 BIT
Figure 43. Timing Register 0
Table 15. TR0 Bit Description
Timing Mode Selection
BLANK Input Control
Pixel Port Control
Timing Register Reset
This bit controls whether the ADV7174/ADV7179 is in master or slave mode.
These bits control the timing mode of the ADV7174/ADV7179. These modes are
described in more detail in the 3.3 V Timing Specifications table.
This bit controls whether the BLANK input is used when the part is in slave mode.
These bits control the addition of a luminance delay. Each bit represents a delay of
This bit is used to set the pixel port to accept 8-bit or YCrCb data on Pins P7–P0.
0 must be written here.
Toggling the TR07 from low to high and to low again resets the internal timing
counters. This bit should be toggled after power-up, reset, or changing to a new
Rev. B | Page 33 of 52
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