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ADV7174KCPZ View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7174KCPZ Chip Scale PAL/NTSC Video Encoder with Advanced Power Management ADI
Analog Devices ADI
ADV7174KCPZ Datasheet PDF : 52 Pages
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ADV7174/ADV7179
TIMING MODE REGISTER 0 (TR0)
Bits:
Address:
TR07–TR00
SR4–SR0 = 07H
Figure 43 shows the various operations under the control of Timing Register 0. This register can be read from as well as written to.
TR07
TR06
TR05
TR04
TR03
TR02
TR01
TR00
TIMING
REGISTER RESET
TR07
BLANK INPUT
CONTROL
TR03
0 ENABLE
1 DISABLE
MASTER/SLAVE
CONTROL
TR00
0 SLAVE TIMING
1 MASTER TIMING
PIXEL PORT
CONTROL
TR06
0 8 BIT
1 FORBIDDEN
LUMA DELAY
TR05 TR04
00
01
10
11
0ns DELAY
74ns DELAY
148ns DELAY
222ns DELAY
TIMING MODE
SELECTION
TR02 TR01
0
0
MODE 0
0
1
MODE 1
1
0
MODE 2
1
1
MODE 3
Figure 43. Timing Register 0
Table 15. TR0 Bit Description
Bit Name
Master/Slave Control
Timing Mode Selection
Bit No.
TR00
TR02–TR01
BLANK Input Control
Luma Delay
TR03
TR05–TR04
Pixel Port Control
TR06
Timing Register Reset
TR07
Description
This bit controls whether the ADV7174/ADV7179 is in master or slave mode.
These bits control the timing mode of the ADV7174/ADV7179. These modes are
described in more detail in the 3.3 V Timing Specifications table.
This bit controls whether the BLANK input is used when the part is in slave mode.
These bits control the addition of a luminance delay. Each bit represents a delay of
74 ns.
This bit is used to set the pixel port to accept 8-bit or YCrCb data on Pins P7–P0.
0 must be written here.
Toggling the TR07 from low to high and to low again resets the internal timing
counters. This bit should be toggled after power-up, reset, or changing to a new
timing mode.
Rev. B | Page 33 of 52
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