ADV7174BCP-REEL View Datasheet(PDF) - Analog Devices
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ADV7174BCP-REEL Datasheet PDF : 52 Pages
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ADV7174/ADV7179
MODE REGISTER 3 (MR3)
Bits:
Address:
MR37–MR30
SR4–SR0 = 03H
Mode Register 3 is an 8-bit-wide register. Figure 41 shows the various operations under the control of Mode Register 3.
MR37
MR36
MR35
MR34
MR33
MR32
MR31
MR30
TTXREQ BIT
MODE CONTROL
MR36
0 NORMAL
1 BIT REQUEST
CHROMA OUTPUT
SELECT
MR34
0 DISABLE
1 ENABLE
VBI_OPEN
MR32
0
1
DISABLE
ENABLE
MR30
MR31
RESERVED
INPUT DEFAULT
COLOR
MR37
0 DISABLE
1 ENABLE
TELETEXT
ENABLE
MR35
0 DISABLE
1 ENABLE
DAC OUTPUT
MR33
DAC A
DAC B
DAC C
0 COMPOSITE
BLUE/COMP/Pb RED/CHROMA/Pr
1 GREEN/LUMA/Y BLUE/COMP/Pb RED/CHROMA/Pr
Figure 41. Mode Register 3
Table 12. MR3 Bit Description
Bit Name
Bit No.
Revision Code
MR30–MR31
VBI Open
MR32
DAC Output
Chroma Output Select
Teletext Enable
TTXREQ Bit Mode Control
Input Default Color
MR33
MR34
MR35
MR36
MR37
Description
These bits are read-only and indicate the revision of the device.
This bit determines whether or not data in the vertical blanking interval (VBI) is output to
the analog outputs or blanked. VBI data insertion is not available in Slave Mode 0. Also,
when both BLANK input control and VBI open are enabled, BLANK input control has
priority, i.e., VBI data insertion will not work.
This bit is used to switch the DAC outputs from SCART to a EUROSCART configuration. A
complete list of all DAC output configurations is shown in Table 13.
With this active high bit it is possible to output an extra chrominance signal C, on DAC A
in any configuration that features a CVBS signal.
This bit must be set to 1 to enable Teletext data insertion on the TTX pin.
This bit enables switching of the Teletext request signal from a continuous high signal
(MR36 = 0) to a bitwise request signal (MR36 = 1).
This bit determines the default output color from the DACs for zero input pixel data (or
disconnected). A Logic 0 means that the color corresponding to 00000000 is displayed. A
Logic 1 forces the output color to black for 00000000 pixel input video data.
Table 13. DAC Output Configuration Matrix
MR34
MR40
MR41
MR33
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
DAC A
CVBS
Y
CVBS
Y
CVBS
G
CVBS
Y
C
Y
C
Y
C
G
C
Y
DAC B
CVBS
CVBS
CVBS
CVBS
B
B
Pb
Pb
CVBS
CVBS
CVBS
CVBS
B
B
Pb
Pb
DAC C
C
C
C
C
R
R
Pr
Pr
C
C
C
C
R
R
Pr
Pr
Rev. B | Page 31 of 52
CVBS: Composite Video Baseband Signal
Y: Luminance Component Signal (For YPbPr or Y/C Mode)
C: Chrominance Signal (For Y/C Mode)
Pb: ColorComponent Signal (For YPbPr Mode)
Pr: Color Component Signal (For YPbPr Mode)
R: RED Component Video (For RGB Mode)
G: GREEN Component Video (For RGB Mode)
B: BLUE Component Video (For RGB Mode)
Each DAC can be powered on or off individually
See MR1 Description and Figure 39.
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