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ADV7174KCPZ View Datasheet(PDF) - Analog Devices

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Description
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ADV7174KCPZ Datasheet PDF : 52 Pages
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ADV7174/ADV7179
MODE REGISTER 1 (MR1)
Bits:
Address:
MR17–MR10
SR4–SR0 = 01H
Figure 39 shows the various operations under the control of Mode Register 1. This register can be read from as well as written to.
MR17
MR16
MR15
MR14
MR13
MR12
MR11
MR10
DAC A
CONTROL
MR16
0 NORMAL
1 POWER-DOWN
RESERVED
1 SHOULD BE
WRITTEN TO
THIS BIT
CLOSED CAPTIONING
FIELD SELECTION
MR12 MR11
0 0 NO DATA OUT
0 1 ODD FIELD ONLY
1 0 EVEN FIELD ONLY
1 1 DATA OUT
(BOTH FIELDS)
COLOR BAR
CONTROL
MR17
0 DISABLE
1 ENABLE
DAC B
CONTROL
MR15
0 NORMAL
1 POWER-DOWN
DAC C
CONTROL
MR13
0 NORMAL
1 POWER-DOWN
INTERLACE
CONTROL
MR10
0 INTERLACED
1 NONINTERLACED
Figure 39. Mode Register 1
Table 10. MR1 Bit Description
Bit Name
Bit No.
Interlace Control
MR10
Closed Captioning Field
Selection
DAC Control
MR12–MR11
MR16–MR15
and MR13
Reserved
Color Bar Control
MR14
MR17
Description
This bit is used to set up the output to interlaced or noninterlaced mode. Power-down mode
is relevant only when the part is in composite video mode.
These bits control the fields on which closed captioning data is displayed; closed captioning
information can be displayed on an odd field, even field, or both fields.
These bits can be used to power down the DACs. Power-down can be used to reduce the
power consumption of the ADV7174/ADV7179 if any of the DACs are not required in the
application.
A Logic 1 must be written to this register.
This bit can be used to generate and output an internal color bar test pattern. The color bar
configuration is 100/7.5/75/7.5 for NTSC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled, the ADV7174/ADV7179 is configured in a master timing mode.
Rev. B | Page 29 of 52
 

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