datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

ADV7174BCP-REEL View Datasheet(PDF) - Analog Devices

Part Name
Description
View to exact match
ADV7174BCP-REEL Datasheet PDF : 52 Pages
First Prev 21 22 23 24 25 26 27 28 29 30 Next Last
ADV7174/ADV7179
Mode 2: Slave Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode, the ADV7174/ADV7179 accepts horizontal and
vertical SYNC signals. A coincident low transition of both and
VSYNC inputs indicates the start of an odd field. A VSYNC low
transition when HSYNC is high indicates the start of an even
field. The BLANK signal is optional. When the BLANK input is
disabled, the ADV7174/ADV7179 automatically blanks all
normally blank lines as per CCIR-624. Mode 2 is illustrated in
Figure 27 (NTSC) and Figure 28 (PAL).
DISPLAY
VERTICAL BLANK
DISPLAY
522 523 524 525
1
2
3
4
HSYNC
BLANK
VSYNC
EVEN FIELD
DISPLAY
5
6
7
8
ODD FIELD
VERTICAL BLANK
9
10
11
20
21
22
DISPLAY
HSYNC
BLANK
VSYNC
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274
ODD FIELD
EVEN FIELD
Figure 27. Timing Mode 2 (NTSC)
283 284 285
DISPLAY
VERTICAL BLANK
DISPLAY
622
623
624
625
1
2
3
4
5
6
7
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
VERTICAL BLANK
21
22
23
DISPLAY
309
310
311
312
313
314
315
316
317
318
319
320
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 28. Timing Mode 2 (PAL)
Rev. B | Page 22 of 52
334
335
336
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]