ADV7174WBCPZ View Datasheet(PDF) - Analog Devices

Part Name

Description

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ADV7174WBCPZ

Chip Scale PAL/NTSC Video Encoder with Advanced Power Management

Analog Devices 

ADV7174/ADV7179

COMPOSITE

VIDEO

(e.g., VCR

OR CABLE)

VIDEO

DECODER

(e.g., ADV7183A)

CLOCK

SCRESET/RTC

GREEN/LUMA/Y

P7–P0

RED/CHROMA/Pr

BLUE/COMPOSITE/Pb

HSYNC

FIELD/VSYNC

AD7174/ADV7179

H/LTRANSITION

COUNT START

4 BITS

RESERVED

LOW

128

14 BITS

RESERVED

13

0

21

FSC PLL INCREMENT1

SEQUENCE

RESERVED

5 BITS

BIT2 RESET

RESERVED

BIT3

0

RTC

TIME SLOT: 01

14 19

NOT USED IN THE

ADV7174/ADV7179

VALID INVALID

SAMPLE SAMPLE

NOTES

1FSC PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7174/ADV7179 FSC DDS REGISTER IS

FSC PLL INCREMENT BITS 21:0 PLUS BITS 0:9 OF THE SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD

BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7174/ADV7179.

2SEQUENCE BIT

PAL: 0 = LINE NORMAL, 1 = LINE INVERTED

NTSC: 0 = NO CHANGE

3RESET BIT

RESET ADV7174/ADV7179 DDS

8/LLC

67 68

Figure 19. RTC Timing and Connections

Vertical Blanking Data Insertion

It is possible to allow encoding of incoming YCbCr data on

those lines of VBI that do not bear line sync or pre-/post-

equalization pulses (see Figure 21 to Figure 32). This mode of

operation is called partial blanking and is selected by setting

MR32 to 1. It allows the insertion of any VBI data (opened VBI)

into the encoded output waveform. This data is present in the

digitized incoming YCbCr data stream, for example. WSS data,

CGMS, VPS, and so on. Alternatively, the entire VBI may be

blanked (no VBI data inserted) on these lines by setting MR32

to 0.

Mode 0 (CCIR-656): Slave Option

(Timing Register 0 TR0 = X X X X X 0 0 0)

The ADV7174/ADV7179 is controlled by the SAV (start active

video) and EAV (end active video) time codes in the pixel data.

All timing information is transmitted using a 4-byte synchro-

nization pattern. A synchronization pattern is sent immediately

before and after each line during active picture and retrace.

Mode 0 is illustrated in Figure 20. The HSYNC, FIELD/VSYNC,

and BLANK (if not used) pins should be tied high during this

mode.

Mode 0 (CCIR-656): Master Option

(Timing Register 0 TR0 = X X X X X 0 0 1)

The ADV7174/ADV7179 generates H, V, and F signals required

for the SAV and EAV time codes in the CCIR-656 standard. The

H bit is output on the HSYNC pin, the V bit is output on the

BLANK pin, and the F bit is output on the FIELD/VSYNC pin.

Mode 0 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL).

The H, V, and F transitions relative to the video waveform are

illustrated in Figure 23.

Rev. B | Page 17 of 52

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