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ADV7177KS View Datasheet(PDF) - Analog Devices

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ADV7177KS Datasheet PDF : 38 Pages
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ADV7177/ADV7178
NTSC PEDESTAL REGISTERS 3–0 (PCE15–0, PCO15–0)
(Subaddress [SR4–SR0] = 11–0EH)
These 8-bit-wide registers are used to set up the NTSC pedestal
on a line-by-line basis in the vertical blanking interval for both
odd and even fields. Figure 40 show the four control registers.
A Logic “1” in any of the bits of these registers has the effect of
turning the pedestal OFF on the equivalent line when used in
NTSC.
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
FIELD 1/3 PCO7 PCO6 PCO5 PCO4 PCO3 PCO2 PCO1 PCO0
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 1/3 PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
FIELD 2/4 PCE7 PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 2/4 PCE15 PCE14 PCE13 PCE12 PCE11 PCE10 PCE9 PCE8
Figure 40. Pedestal Control Registers
MODE REGISTER 3 MR3 (MR37–MR30)
(Address [SR4–SR0] = 12H)
Mode Register 3 is an 8-bit-wide register.
Figure 41 shows the various operations under the control of
Mode Register 3.
MR3 BIT DESCRIPTION
Revision Code (MR30)
This bit is read only and indicates the revision of the device.
VBI Pass-Through Control (MR31)
This bit determines whether or not data in the vertical blanking
interval (VBI) is output to the analog outputs or blanked.
Clock Output Select (MR33–MR32)
These bits control the synchronous clock output signal. The
clock can be 27 MHz, 13.5 MHz or disabled, depending on the
values of these bits.
OSD Enable (MR35)
A logic one in MR35 will enable the OSD function on the
ADV7177.
Reserved (MR36)
These bits are reserved.
Input Default Color (MR36)
This bit determines the default output color from the DACs for
zero input data (or disconnected). A Logical “0” means that the
color corresponding to 00000000 will be displayed. A Logical
“1” forces the output color to black for 00000000 input video
data.
OSD REGISTER 0–11
(Address [SR4–SR0] = 12H–1DH)
There are 12 OSD registers as shown in Figure 42. There are
four bits for each Y, Cb and Cr value, there are four zero added
to give the complete byte for each value loaded internally.
(Y0 = [Y03, Y02, Y01, Y00, 0, 0, 0, 0], Cb = [Cb3, Cb2, Cb1,
Cb0, 0, 0, 0, 0,], Cr = [Cr3, Cr2, Cr1, Cr0, 0, 0, 0, 0].)
MR37
MR36
MR35
MR34
MR33
MR32
MR31
MR30
MR37
ZERO SHOULD
BE WRITTEN TO
THIS BIT
OSD ENABLE
MR35
0
DISABLE
1
ENABLE
CLOCK CONTROL
MR33-32
0 0 CLOCK OUTPUT OFF
0 1 13.5MHz OUTPUT
1 0 27MHz OUTPUT
1 1 CLOCK OUTPUT OFF
MR30
REV CODE
(READ ONLY)
INPUT DEFAULT COLOR
MR36
0 INPUT COLOR
1 BLACK
MR34
ZERO SHOULD
BE WRITTEN TO
THIS BIT
VBI PASSTHROUGH
MR31
0
DISABLE
1
ENABLE
Figure 41. Mode Register 3
OSD
REG 0
OSD
REG 1
OSD
REG 2
OSD
REG 11
Y0
Cb0
Cr1
Cr0
Y1
Cb1
Cr7
Cb7
Figure 42. OSD Registers
REV. 0
–27–
 

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