ADV7177KS View Datasheet(PDF) - Analog Devices
Part Name
Description
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ADV7177KS Datasheet PDF : 38 Pages
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ADV7177/ADV7178
MR17
MR16
MR15
MR14
MR13
MR12
MR11
MR10
MR16
(1)
ONE SHOULD
BE WRITTEN TO
THIS BIT
LUMA
DAC CONTROL
MR14
0 NORMAL
1 POWER-DOWN
CLOSED CAPTIONING
FIELD SELECTION
MR12 MR11
0 0 NO DATA OUT
0 1 ODD FIELD ONLY
1 0 EVEN FIELD ONLY
1 1 DATA OUT
(BOTH FIELDS)
COLOR BAR
CONTROL
MR17
0 DISABLE
1 ENABLE
COMPOSITE
DAC CONTROL
MR15
0 NORMAL
1 POWER-DOWN
CHROMA
DAC CONTROL
MR13
0 NORMAL
1 POWER-DOWN
INTERLACE
CONTROL
MR10
0 INTERLACED
1 NONINTERLACED
Figure 33. Mode Register 1 (MR1)
RGB Sync (MR05)
This bit is used to set up the RGB outputs with the sync infor-
mation encoded on all RGB outputs.
Output Control (MR06)
This bit specifies if the part is in composite video or RGB/YUV
mode. Please note that the main composite signal is still avail-
able in RGB/YUV mode.
MODE REGISTER 1 MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)
Figure 33 shows the various operations under the control of Mode
Register 1. This register can be read from as well as written to.
MR1 BIT DESCRIPTION
Interlaced Mode Control (MR10)
This bit is used to set up the output to interlaced or noninter-
laced mode. This mode is only relevant when the part is in
composite video mode.
Closed Captioning Field Control (MR12–MR11)
These bits control the fields on which closed captioning data is
displayed; closed captioning information can be displayed on an
odd field, even field or both fields.
DAC Control (MR15–MR13)
These bits can be used to power down the DACs. This can
be used to reduce the power consumption of the ADV7177/
ADV7178 if any of the DACs are not required in the application.
Color Bar Control (MR17)
This bit can be used to generate and output an internal color
bar test pattern. The color bar configuration is 75/7.5/75/7.5
for NTSC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled the ADV7177/ADV7178 is config-
ured in a master timing mode as per the one selected by bits
TR01 and TR02.
SUBCARRIER FREQUENCY REGISTER 3-0
(FSC3–FSC0)
(Address [SR4–SR0] = 05H–02H)
These 8-bit-wide registers are used to set up the subcarrier
frequency. The value of these registers are calculated by using
the following equation:
Subcarrier Frequency Register
=
232 –1×
FCLK
FSCF
i.e.: NTSC Mode,
FCLK = 27 MHz,
FSCF = 3.5795454 MHz
Subcarrier Frequency Value
=
232 – 1
27 × 106
× 3.5795454 × 106
= 21F07C16 HEX
Figure 34 shows how the frequency is set up by the four registers.
SUBCARRIER
FREQUENCY
REG 3
SUBCARRIER
FREQUENCY
REG 2
SUBCARRIER
FREQUENCY
REG 1
SUBCARRIER
FREQUENCY
REG 0
FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16
FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8
FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0
Figure 34. Subcarrier Frequency Register
SUBCARRIER PHASE REGISTER (FP7–FP0)
(Address [SR4–SR0] = 06H)
This 8-bit-wide register is used to set up the subcarrier phase.
Each bit represents 1.41 degrees.
TIMING REGISTER 0 (TR07–TR00)
(Address [SR4–SR0] = 07H)
Figure 35 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to. This register can be used to adjust the width and
position of the master mode timing signals.
TR0 BIT DESCRIPTION
Master/Slave Control (TR00)
This bit controls whether the ADV7177/ADV7178 is in master
or slave mode. This register can be used to adjust the width and
position of the master timing signals.
Timing Mode Control (TR02–TR01)
These bits control the timing mode of the ADV7177/ADV7178.
These modes are described in the Timing and Control section
of the data sheet.
BLANK Control (TR03)
This bit controls whether the BLANK input is used when the
part is in slave mode
–24–
REV. 0
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