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ADV7173 View Datasheet(PDF) - Analog Devices

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ADV7172/ADV7173
5 V TIMING SPECIFICATIONS (VAA = 5 V ؎ 5%1, VREF = 1.235 V, RSET1 = 600 unless otherwise noted. All specifications TMIN
to TMAX2 unless otherwise noted.)
Parameter
Conditions
Min Typ Max Unit
MPU PORT3, 4
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
ANALOG OUTPUTS3, 5
Analog Output Delay
DAC Analog Output Skew
After this period the 1st clock is generated
relevant for repeated Start Condition.
0
0.6
1.3
0.6
0.6
100
0.6
7
0
400 kHz
µs
µs
µs
µs
ns
300 ns
300 ns
µs
ns
ns
CLOCK CONTROL AND
PIXEL PORT5, 6
fCLOCK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, t15
TELETEXT PORT3, 7
Digital Output Access Time, t16
Data Setup Time, t17
Data Hold Time, t18
RESET CONTROL3
RESET Low Time
27
MHz
8
ns
8
ns
4.0
ns
5.0
ns
4
ns
3
ns
15
24
ns
10
ns
37
Clock Cycles
20
ns
2
ns
6
ns
3
ns
NOTES
1The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.
2Temperature range TMIN to TMAX: 0°C to 70°C.
3TTL input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load 10 pF.
4Guaranteed by characterization.
5Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6Pixel Port consists of the following:
Pixel Inputs:
Pixel Controls:
P7–P0
HSYNC, FIELD/VSYNC, BLANK, VSO, CSO_HSO, CLAMP
Clock Input:
CLOCK
7Teletext Port consists of the following:
Teletext Output:
TTXREQ
Teletext Input:
TTX
Specifications subject to change without notice.
–6–
REV. B
 

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