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ADV7172KST View Datasheet(PDF) - Analog Devices

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ADV7172KST Datasheet PDF : 60 Pages
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ADV7172/ADV7173
CGMS_WSS REGISTER 1 C/W1 (C/W17–C/W10)
(Address (SR4–SR0) = 1AH)
CGMS_WSS Register 1 is an 8-bit-wide register. Figure 61 shows
the operations under control of this register.
C/W1 BIT DESCRIPTION
CGMS/WSS Data (C/W15–C/W10)
These bit locations are shared by CGMS data and WSS data. In
NTSC mode these bits are CGMS data. In PAL mode these
bits are WSS data.
CGMS Data Only (C/W17–C/W16)
These bits are CGMS data bits only.
CGMS_WSS REGISTER 2 C/W1(C/W27–C/W20)
(Address (SR4-SR0) = 1BH)
CGMS_WSS Register 2 is an 8-bit-wide register. Figure 62
shows the operations under control of this register.
C/S BIT DESCRIPTION
CGMS/WSS Data (C/W27–C/W20)
These bit locations are shared by CGMS data and WSS data. In
NTSC mode these bits are CGMS data. In PAL mode these
bits are WSS data.
CONTRAST CONTROL REGISTER (CC07–CC00)
(Address (SR4–SR0) = 1DH)
The contrast control register is an 8-bit-wide register used to
scale the Y output levels. Figure 63 shows the operations under
control of this register.
CC0 BIT DESCRIPTION
Reserved (CC07–CC06)
A Logic “0” must be written to these bits.
Y Scalar Value (CC05–CC00)
These six bits represent the value required to scale the Y pixel
data from 0.75 to 1.25 of its initial level. The value of these six
bits is calculated using the following equation:
Contrast Control Register = (X –0.785) × 128
where X = Scaling factor for Y
e.g., Scale Y by 0.9
Contrast Control Register = (0.9–0.75) × 128 = 19.2 = 010011
(rounded to the nearest integer)
Actual scaling factor = 0.898.
C/W17
C/W16
C/W15
C/W14
C/W13
C/W12
C/W11
C/W10
C/W17C/W16
CGMS DATA
C/W15C/W10
CGMS/WSS DATA
Figure 61. CGMS_WSS Register 1
C/W27
C/W26
C/W25
C/W24
C/W23
C/W22
C/W21
C/W20
C/W27C/W20
CGMS/WSS DATA
Figure 62. CGMS_WSS Register 2
CC07
CC06
CC05
CC04
CC03
CC02
CC01
CC07CC06
ZERO SHOULD
BE WRITTEN
TO THESE BITS
CC05CC00
Y SCALAR VALUE
Figure 63. Contrast Control Register
CC00
–38–
REV. B
 

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