ADV7172KST View Datasheet(PDF) - Analog Devices

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ADV7172KST

Digital PAL/NTSC Video Encoder with Six DACs (10 Bits), Color Control and Enhanced Power Management

Analog Devices 

ADV7172/ADV7173

MODE REGISTER 6 MR6 (MR67–MR60)

(Address (SR4–SR0) = 06H)

Mode Register 6 is an 8-bit-wide register. Figure 50 shows the

various operations under the control of Mode Register 6.

MR6 BIT DESCRIPTION

Power-Up Sleep Mode Control (MR60)

After reset this bit is set to “0,” if both SCRESET/RTC and

NTSC_PAL pins are tied high, the part will power-up in sleep

mode (to facilitate low power consumption before the I2C is

initialized). When this bit is set to “1” (via the I2C), sleep mode

control passes to Mode Register 2, Bit 7.

Reserved (MR61)

A Logic “0” must be written to this bit.

Luma Autodetect Control (MR62)

This bit controls which mode of autodetect operation is being

used on the luma DAC (DAC B) on the ADV7172/ADV7173.

If this bit is set (“0”), Mode 0 is on; if this bit is set (“1”), then

Mode 1 is being used.

Composite Autodetect Control (MR63)

This bit controls which mode of autodetect operation is being

used on the composite DAC (DAC A) on the ADV7172/

ADV7173. If this bit is set (“0”), Mode 0 is on; if this bit is set

(“1”), then Mode 1 is being used.

DAC Termination Control (MR64)

This bit controls the load termination resistance detected by the

autodetect functionality. If this bit is set (“0”), the autodetect

feature is used to determine if a 75 Ω termination is present. If

this bit is set to (“1”), the autodetect feature is used to indicate

if a 150 Ω termination is present.

Reserved (MR65)

A Logic “0” must be written to this bit.

Luma DAC Status Bit (MR66)

This bit is a read-only status bit for the autodetect feature of

the ADV7172/ADV7173 and may be read to check whether

or not the composite DAC is terminated. If this bit is set (“1”),

there is no termination; if this bit is set (“0”), the composite DAC

is terminated.

Composite DAC Status Bit (MR67)

This bit is a read only status bit for the autodetect feature of the

ADV7172/ADV7173 and may be read to check whether or not

the luma DAC is terminated. If this bit is set (“1”), there is no

termination. If this bit is set (“0”), the luma DAC is terminated.

MR67

MR66

MR65

MR64

MR63

MR62

MR61

MR60

COMPOSITE

DAC STATUS BIT

MR67

0 NOT TERMINATED

1 TERMINATED

MR65

ZERO SHOULD

BE WRITTEN TO

THIS BIT

COMP AUTODETECT

CONTROL

MR63

0 MODE 0

1 MODE 1

MR61

ZERO SHOULD

BE WRITTEN TO

THIS BIT

LUMA DAC

STATUS BIT

MR66

0 NOT TERMINATED

1 TERMINATED

DAC TERMINATION

CONTROL

MR64

0 1 ؋ MODE

1 2 ؋ MODE

LUMA AUTODETECT

CONTROL

MR62

0 MODE 0

1 MODE 1

Figure 50. Mode Register 6 (MR6)

POWER-UP SLEEP

MODE CONTROL

MR60

0 ENABLE

1 DISABLE

–32–

REV. B

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