ADV7172/ADV7173
Mode 0 (CCIR–656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7172/ADV7173 generates H, V, and F signals required for the SAV (Start Active Video) and EAV (End Active Video)
Time Codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit
is output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL). The H, V, and F transitions
relative to the video waveform are illustrated in Figure 26.
DISPLAY
VERTICAL BLANK
DISPLAY
522 523 524 525
1
H
2
3
4
5
6
7
V
F
EVEN FIELD ODD FIELD
8
9
10
11
DISPLAY
VERTICAL BLANK
20
21
22
DISPLAY
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274
H
V
F
ODD FIELD EVEN FIELD
Figure 24. Timing Mode 0 (NTSC Master Mode)
DISPLAY
VERTICAL BLANK
283 284 285
DISPLAY
622
623
624
625
1
2
3
4
5
6
7
H
V
F
EVEN FIELD ODD FIELD
DISPLAY
VERTICAL BLANK
21
22
23
DISPLAY
309
310
311
312
313
314
315
316
317
318
319
320
H
V
F
ODD FIELD EVEN FIELD
Figure 25. Timing Mode 0 (PAL Master Mode)
REV. B
–17–
334
335
336