ADV7170/ADV7171
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
+5V (VAA)
+5V (VAA)
0.1F
0.1F
25 COMP
0.1F
1, 11, 20, 28, 30
VAA
0.01F
+5V (VAA)
L1
(FERRITE BEAD)
10F
33F
+5V (VAA)
33 VREF
38–42,
2–9, 12–14
DAC D 27
ADV7170/
ADV7171
P15–P0
DAC C 26
RESET
4k⍀
100nF
+5V (VAA)
100k⍀
TTX
TTXREQ
100k⍀
“UNUSED
INPUTS
SHOULD BE
GROUNDED”
TELETEXT PULL-UP AND
PULL-DOWN RESISTORS
SHOULD ONLY BE USED
IF THESE PINS ARE NOT
CONNECTED
27MHz CLOCK
(SAME CLOCK AS USED BY
MPEG2 DECODER)
35 SCRESET/RTC
15 HSYNC
16 FIELD/VSYNC
17 BLANK
22 RESET
DAC B 31
DAC A 32
37 TTX
36 TTXREQ
+5V (VAA)
10k⍀
44 CLOCK
ALSB
18
SCLOCK 23
SDATA 24
RSET 34
GND
10, 19, 21
29, 43
75⍀
75⍀
S VIDEO
75⍀
75⍀
100⍀
100⍀
+5V (VCC) +5V (VCC)
5k⍀
5k⍀
MPU BUS
150⍀
Figure 54. Recommended Analog Circuit Layout
+5V
(VCC)
GND
The circuit below can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the HSYNC pulse. This waveform
is guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. This 13.5 MHz clock can be used if
13.5 MHz clock is required by the MPEG decoder. This will guarantee that the Cr and Cb pixel information is input to the
ADV7170/ADV7171 in the correct sequence.
CLOCK
HSYNC
D
Q
CK
D
Q
CK
13.5MHz
Figure 55. Circuit to Generate 13.5 MHz
REV. 0
–31–