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ADV7171KSUZ-REEL View Datasheet(PDF) - Analog Devices

Part Name
Description
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ADV7171KSUZ-REEL Datasheet PDF : 64 Pages
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ADV7170/ADV7171
MR07
MR06
MR05
MR04
MR03
MR02
MR01
MR00
MR07
0
0
0
0
1
1
1
1
CHROMA FILTER SELECT
MR06 MR05
0
0
1.3MHz LOW PASS FILTER
0
1
0.65MHz LOW PASS FILTER
1
0
1.0MHz LOW PASS FILTER
1
1
2.0MHz LOW PASS FILTER
0
0
RESERVED
0
1
CIF
1
0
Q CIF
1
1
RESERVED
OUTPUT VIDEO
STANDARD SELECTION
MR01 MR00
0
0
NTSC
0
1
PAL (B, D, G, H, I)
1
0
PAL (M)
1
1
RESERVED
MR04
0
0
0
0
1
1
1
1
LUMA FILTER SELECT
MR03 MR02
0
0
LOW PASS FILTER (NTSC)
0
1
LOW PASS FILTER (PAL)
1
0
NOTCH FILTER (NTSC)
0
1
NOTCH FILTER (PAL)
0
0
EXTENDED MODE
0
1
CIF
1
0
Q CIF
1
1
RESERVED
Figure 38. Mode Register 0
MODE REGISTER 1 MR1 (MR17 TO MR10)
(Address (SR4 to SR0) = 01H)
Figure 39 shows the various operations under the control of
Mode Register 1. This register can be read from as well as
written to.
Color Bar Control (MR17)
This bit can be used to generate and output an internal color bar
test pattern. The color bar configuration is 100/7.5/75/7.5 for
NTSC and 100/0/75/0 for PAL. It is important to note that when
color bars are enabled, the ADV7170/ADV7171 are configured
in a master timing mode.
MR1 BIT DESCRIPTION
Interlace Control (MR10)
This bit is used to set up the output to interlaced or noninter-
laced mode. This mode is only relevant when the part is in
composite video mode.
Closed Captioning Field Selection (MR12 to MR11)
These bits control the fields on which closed captioning data is
displayed. Closed captioning information can be displayed on
an odd field, even field, or both odd and even fields.
DAC Control (MR16 to MR13)
These bits can be used to power down the DACs. This can be
used to reduce the power consumption of the ADV7170/
ADV7171 if any of the DACs are not required in the
application.
MODE REGISTER 2 MR2 (MR27 TO MR20)
(Address [SR4 to SR0] = 02H)
Mode Register 2 is an 8-bit-wide register.
Figure 40 shows the various operations under the control of
Mode Register 2. This register can be read from as well as
written to.
MR2 BIT DESCRIPTION
Square Pixel Control (MR20)
This bit is used to set up square pixel mode. This is available in
slave mode only. For NTSC, a 24.5454 MHz clock must be
supplied. For PAL, a 29.5 MHz clock must be supplied.
Rev. C | Page 30 of 64
 

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