ADV7171KSUZ-REEL View Datasheet(PDF) - Analog Devices

Part Name

Description

View to exact match

ADV7171KSUZ-REEL

Digital PAL/NTSC Video Encoder with 10-Bit SSAF™ and Advanced Power Management

Analog Devices 

ADV7170/ADV7171

Mode 1: Master Option HSYNC, BLANK, FIELD

(Timing Register 0 TR0 = X X X X X 0 1 1)

In this mode the ADV7170/ADV7171 can generate horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when

HSYNC is low indicates a new frame, that is, vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the

ADV7170/ADV7171 automatically blank all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following

the timing signal transitions. Mode 1 is shown in Figure 24 (NTSC) and Figure 25 (PAL). Figure 26 illustrates the HSYNC, BLANK, and

FIELD for an odd or even field transition relative to the pixel data.

HSYNC

FIELD

BLANK

PAL = 12 × CLOCK/2

NTSC = 16 × CLOCK/2

PIXEL

DATA

Cb Y Cr Y

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 26. Timing Mode 1 Odd/Even Field Transitions Master/Slave

Mode 2: Slave Option HSYNC, VSYNC, BLANK

(Timing Register 0 TR0 = X X X X X 1 0 0)

In this mode the ADV7170/ADV7171 accept horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and

VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The

BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blank all normally blank lines as

per CCIR-624. Mode 2 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL).

DISPLAY

VERTICAL BLANK

DISPLAY

522 523 524 525

1

HSYNC

BLANK

VSYNC

DISPLAY

2

3

4

EVEN FIELD

5

6

7

8

ODD FIELD

VERTICAL BLANK

9

10

11

20

21

22

DISPLAY

HSYNC

BLANK

VSYNC

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

ODD FIELD

EVEN FIELD

Figure 27. Timing Mode 2 (NTSC)

Rev. C | Page 23 of 64

283 284 285

Share Link: