ADV7150 View Datasheet(PDF) - Analog Devices
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ADV7150 Datasheet PDF : 36 Pages
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ADV7150
Example 2
Color Mode
Multiplexing
Databus
RAM-DAC Resolution
SYNC
Pedestal
Calibration
24-Bit Gamma Corrected True Color (30 Bits)
2:1
10 Bit
10 Bit
Ignored
0 IRE
Every Vertical Sync
Register Initialization
C1
Write 0FH to Mode Register (MR1)
1
Write 0EH to Mode Register (MR1)
1
Write 0FH to Mode Register (MR1)
1
Write 2FH to Mode Register (MR1)
1
Write 0FH to Mode Register (MR1)
1
Write 04H to Address Register (A7–A0)
0
Write FFH to Pixel Mask Register
1
Write 05H to Address Register (A7–A0)
0
Write 01H to Command Reg 1 (CR1)
0
Write 06H to Address Register (A7–A0)
0
Write E0H to Command Reg 2 (CR2)
1
Write 07H to Address Register (A7–A0)
0
Write 41H to Command Reg 3 (CR3)
1
Color Palette RAM Initialization
C1
Write 00H to Address Register (A7–A0)
0
Write 000H (Red Data) to RAM Location (00H) 0
Write 000H (Green Data) to RAM Location (00H) 0
Write 000H (Blue Data) to RAM Location (00H) 0
Write xxxH (Red Data) to RAM Location (01H) 0
Write xxxH (Green Data) to RAM Location (01H) 0
Write xxxH (Blue Data) to RAM Location (01H) 0
•
•
•
•
•
•
•
•
•
•
•
•
Write 3FFH (Red Data) to RAM Location (FFH) 0
Write 3FFH (Green Data) to RAM Location (FFH) 0
Write 3FFH (Blue Data) to RAM Location (FFH) 0
C0 R/W Comment
10
Resets to Normal Operation, 10-Bit Bus/RAM-DAC
1 0 *(Initializes Pipelining
10
*( “
10
*(Calibrates LOADOUT/LOADIN Timing
10
*( “
0 0 Address Reg Points to Pixel Mask Register
0 0 Sets the Pixel Mask to All “1s”
0 0 Address Reg Points to Command Register 1 (CR1)
0 0 Calibrates Every Vertical Sync
0 0 Address Reg Points to Command Register 2 (CR2)
00
Sets 24-Bit Color, 0 IRE, No SYNC
0 0 Address Reg Points to Command Register 3 (CR3)
0 0 Sets 2:1 Multiplexing, PRGCKOUT = CLOCK/8
C0 R/W Comment
0 0 Points to Color Palette RAM
10
(Initializes Palette RAM
1 0 ( to a “Gamma” Ramp**
10
(
10
(
10
(
10 (
••
(
••
(
10
(
10
(
1 0 (RAM Initialization Complete
**These four command lines reset the ADV7150 The pipelines for each of the Red, Green and Blue pixel inputs are synchronously reset to the Multiplexer’s “A” in-
put. Mode Register bit MR10 is written by a “1” followed by “0” followed by “1.” LOADIN/LOADOUT timing is internally synchronized by writing a “0” followed
by a “1” followed by a “0” to Mode Register MR15.
**Data for a gamma curve characteristic is obtainable in Appendix 3.
REGISTER DIAGNOSTIC TESTING
The previous examples show the register initialization sequence
for the ADV7150. These show control data going to the regis-
ters and palette RAM. As well as this writing function, it may
also be necessary, due to system diagnostic requirements, to
confirm that correct data has been transferred to each register
and palette RAM location. There are two ways to incorporate
register value/RAM value checking:
1. READ after each WRITE: After data is written to a particular
register, it can be read back immediately. The following table
shows an example with Command Registers CR2 and CR3.
C1 C0
00
10
10
00
10
10
R/W D0–D7
0 06H
0 E0H
1 E0H
0 07H
0 40H
1 40H
Comment
Select Command Register 2 (CR2)
Sets 24-Bit True-Color
Command Reg 2 Value Read-Back
Select Command Register 3 (CR3)
Set 2:1 Mux Mode
Command Reg 3 Value Read-Back
2. READ after all WRITEs completed: All registers and the
color palette RAM are written to and set. Once this is
complete, all registers are again accessed but this time in
Read-Only mode. The table below shows this method for
Command Registers CR2 and CR3.
C1 C0 R/W D0–D7 Comment
0 0 0 06H Select Command Register 2 (CR2)
1 0 0 E0H Sets 24-Bit True-Color
0 0 0 07H Select Command Register 3 (CR3)
1 0 0 40H Set 2:1 Mux Mode
0 0 0 06H Select CR2
1 0 1 E0H CR2 Value Read-Back
0 0 0 07H Select CR3
1 0 1 40H CR3 Value Read-Back
1 0 1 40H CR3 Value Read-Back
It is clear that this latter case requires more command lines
than the previous READ after each WRITE case.
REV. A
–31–
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