CLOCK, CLOCK Inputs
The Clock Control Circuit is driven by the pixel clock inputs,
CLOCK and CLOCK. These inputs can be driven by a differ-
ential ECL oscillator running from a +5 V supply.
Alternatively, the ADV7150 CLOCK inputs can be driven by a
Programmable Clock Generator (Figure 15), such as the
ICS1562. The ICS1562 is a monolithic, phase-locked-loop,
clock generator chip. It is capable of synthesizing differential
ECL output frequencies in a range up to 220 MHz from a single
low frequency reference crystal.
D0-D3 CS R/W
Figure 15. PLL Generator Driving CLOCK, CLOCK of the
CLOCK CONTROL SIGNALS
The ADV7150 generates a LOADOUT control signal which
runs at a divided down frequency of the pixel CLOCK. The
frequency is automatically set to the programmed multiplex
rate, controlled by CR37 and CR36 of Command Register 3.
fLOADOUT = fCLOCK/4
fLOADOUT = fCLOCK/2
fLOADOUT = fCLOCK
4:1 Multiplex Mode
2:1 Multiplex Mode
1:1 Multiplex Mode
The LOADOUT signal is used to directly drive the LOADIN
pixel latch signal of the ADV7150. This is most simply achieved
by tying the LOADOUT and LOADIN pins together. Alterna-
tively, the LOADOUT signal can be used to drive the frame
buffer’s shift clock signals, returning to the LOADIN input de-
layed with respect to LOADOUT.
If it is not necessary to have a known fixed number of pipeline
delays, then there is no limitation on the delay between LOAD-
OUT and LOADIN (LOADOUT(1) and LOADOUT(2)).
LOADIN and Pixel Data must conform to the setup and hold
times (t8 and t9).
If, however, it is required that the ADV7150 has a fixed number
of pipeline delays (tPD), LOADOUT and LOADIN must con-
form to timing specifications t10 and τ-t11 as illustrated in Fig-
ures 4 to 7.
Figure 16. LOADOUT vs. Pixel Clock Input (CLOCK, CLOCK)
The PRGCKOUT control signal outputs a user programmable
clock frequency. It is a divided down frequency of the pixel
CLOCK (see Figure 8). The rising edge of PRGCKOUT is
synchronous to the rising edge of LOADOUT
fPRGCKOUT = fCLOCK/N
where N = 4, 8, 16 or 32.
One application of the PRGCKOUT is to use it as the master
clock frequency of the graphics subsystems processor or
These video memory signals are used to minimize external sup-
port chips. Figure 17 illustrates the function that is provided.
An input signal applied to SCKIN is synchronously AND-ed
with the video blanking signal (BLANK). The resulting signal is
output on SCKOUT. Figure 9 of the Timing Waveform section
shows the relationship between SCKOUT, SCKIN and BLANK.
Figure 17. SCKOUT Generation Circuit
The SCKOUT signal is essentially the video memory shift con-
trol signal. It is stopped during the screen retrace. Figure 18
shows a suggested frame buffer to ADV7150 interface. This is a
minimum chip solution and allows the ADV7150 control the
overall graphics system clocking and synchronization.
Figure 18. ADV7150 Interface Using SCKIN and SCKOUT