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ADV7150LS220 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7150LS220 CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC ADI
Analog Devices ADI
ADV7150LS220 Datasheet PDF : 36 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADV7150
Mnemonic
RED (R0A . . . R0D–R7A . . . R7D),
GREEN (G0A . . . G0D–G7A. . . G7D),
BLUE (B0A . . . B0D–B7A . . . B7D)
PS0A . . . PS0D, PS1A . . . PS1D
LOADIN
LOADOUT
PRGCKOUT
SCKIN
SCKOUT
CLOCK, CLOCK
BLANK
SYNC
SYNCOUT
D0–D9
CE
PIN FUNCTION DESCRIPTION
Function
Pixel Port (TTL Compatible Inputs): 96 pixel select inputs, with 8 bits each for Red, 8
bits for Green and 8 bits for Blue. Each bit is multiplexed [A-D] 4:1, 2:1 or 1:1. It can
be configured for 24-Bit True-Color Data, 8-Bit Pseudo-Color Data and 15-Bit True-Color
Data formats. Pixel Data is latched into the device on the rising edge of LOADIN.
Palette Priority Selects (TTL Compatible Inputs): These pixel port select inputs deter-
mine whether or not the device’s pixel data port is selected on a pixel by pixel basis.
The palette selects allow switching between multiple palette devices. The device can be
preprogrammed to completely shut off the DAC analog outputs. If the values of PS0
and PS1 match the values programmed into bits MR16 and MR17 of the Mode Regis-
ter, then the device is selected. Each bit is multiplexed [A-D] 4:1, 2:1 or 1:1. PS0 and
PS1 are latched into the device on the rising edge of LOADIN.
Pixel Data Load Input (TTL Compatible Input). This input latches the multiplexed
pixel data, including PS0–PS1, BLANK and SYNC into the device.
Pixel Data Load Output (TTL Compatible Output). This output control signal runs at
a divided down frequency of the pixel CLOCK input. Its frequency is a function of the
multiplex rate. It can be used to directly or indirectly drive LOADIN
fLOADOUT = fCLOCK/M
where M = 1 for 1:1 Multiplex Mode
where M = 2 for 2:1 Multiplex Mode
where M = 4 for 4:1 Multiplex Mode.
Programmable Clock Output (TTL Compatible Output). This output control signal
runs at a divided down frequency of the pixel CLOCK input. Its frequency is user
programmable and is determined by bits CR30 and CR31 of Command Register 3
where N = 4, 8, 16 and 32.
fPRGCKOUT = fCLOCK/N
Video Shift Clock Input (TTL Compatible Input). The signal on this input is internally
gated synchronously with the BLANK signal. The resultant output, SCKOUT, is a
video clocking signal that is stopped during video blanking periods.
Video Shift Clock Output (TTL Compatible Output). This output is a synchronously
gated version of SCKIN and BLANK. SCKOUT, is a video clocking signal that is
stopped during video blanking periods.
Clock Inputs (ECL Compatible Inputs). These differential clock inputs are designed to
be driven by ECL logic levels configured for single supply (+5 V) operation. The clock
rate is normally the pixel clock rate of the system.
Composite Blank (TTL Compatible Input). This video control signal drives the analog
outputs to the blanking level.
Composite-Sync Input (TTL Compatible Input). This video control signal drives the
IOG analog output to the SYNC level. It is only asserted during the blanking period.
CR22 in Command Register 2 must be set if SYNC is to be decoded onto the analog
output, otherwise the SYNC input is ignored.
Composite-Sync Output (TTL Compatible Output). This video output is a delayed
version of SYNC. The delay corresponds to the number of pipeline stages of the device.
Databus (TTL Compatible Input/Output Bus). Data, including color palette values and
device control information is written to and read from the device over this 10-bit, bidi-
rectional databus. 10-bit data or 8-bit data can be used. The databus can be configured
for either 10-bit parallel data or byte data (8+2) as well as standard 8-bit data. Any un-
used bits of the databus should be terminated through a resistor to either the digital
power plane (VCC) or GND.
Chip Enable (TTL Compatible Input). This input must be at Logic “0,” when writing
to or reading from the device over the databus (D0–D9). Internally, data is latched on
the rising edge of CE.
–10–
REV. A
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