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ADV7125WBSTZ170-RL View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7125WBSTZ170-RL CMOS, 330 MHz Triple 8-Bit High Speed Video DAC ADI
Analog Devices ADI
ADV7125WBSTZ170-RL Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Pin Number
37
Mnemonic
RSET
38
49 (EPAD)
PSAVE
EP (EPAD)
ADV7125
Description
A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video
signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. The
relationship between RSET and the full-scale output current on IOG (assuming ISYNC is connected to IOG)
is given by:
RSET (Ω) = 11,445 × VREF (V)/IOG (mA)
The relationship between RSET and the full-scale output current on IOR, IOG, and IOB is given by:
IOG (mA) = 11,444.8 × VREF (V)/RSET (Ω) (SYNC being asserted)
IOR, IOB (mA) = 7989.6 × VREF (V)/RSET (Ω)
The equation for IOG is the same as that for IOR and IOB when SYNC is not being used, that is, SYNC
tied permanently low.
Power Save Control Pin. Reduced power consumption is available on the ADV7125 when this pin is
active.
The LFCSP_VQ has an exposed paddle that must be connected to GND.
Rev. C | Page 9 of 16
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