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ADV7125WBCPZ170-RL View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7125WBCPZ170-RL CMOS, 330 MHz Triple 8-Bit High Speed Video DAC ADI
Analog Devices ADI
ADV7125WBCPZ170-RL Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADV7125
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND 1
GND 2
G0 3
G1 4
G2 5
G3 6
G4 7
G5 8
G6 9
G7 10
BLANK 11
SYNC 12
PIN 1
INDICATOR
ADV7125
TOP VIEW
(Not to Scale)
36 VREF
35 COMP
34 IOR
33 IOR
32 IOG
31 IOG
30 VAA
29 VAA
28 IOB
27 IOB
26 GND
25 GND
NOTES
1. THE LFCSP_VQ HAS AN EXPOSED PADDLE THAT MUST BE
CONNECTED TO GND.
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin Number Mnemonic
Description
1, 2, 14, 15, 25, GND
26, 39, 40
Ground. All GND pins must be connected.
3 to 10, 16 to
23, 41 to 48
G0 to G7,
B0 to B7,
R0 to R7
Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of
CLOCK. R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should be
connected to either the regular printed circuit board (PCB) power or ground plane.
11
BLANK
Composite Blank Control Input (TTL Compatible). A Logic 0 on this control input drives the analog
outputs, IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the rising edge of
CLOCK. While BLANK is a Logic 0, the R0 to R7, G0 to G7, and B0 to B7 pixel inputs are ignored.
12
SYNC
Composite Sync Control Input (TTL Compatible). A Logic 0 on the SYNC input switches off a
40 IRE current source. This is internally connected to the IOG analog output. SYNC does not override
any other control or data input; therefore, it should only be asserted during the blanking interval.
SYNC is latched on the rising edge of CLOCK. If sync information is not required on the green channel,
the SYNC input should be tied to Logic 0.
13, 29, 30
24
VAA
CLOCK
Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7125 must be connected.
Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0 to R7, G0 to G7, B0 to B7, SYNC,
and BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK
should be driven by a dedicated TTL buffer.
33, 31, 27
IOR, IOG, IOB
Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These RGB video
outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω
load. If the complementary outputs are not required, these outputs should be tied to ground.
34, 32, 28
IOR, IOG, IOB
Red, Green, and Blue Current Outputs. These high impedance current sources are capable of directly
driving a doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output
loads whether or not they are all being used.
35
COMP
Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 μF ceramic
capacitor must be connected between COMP and VAA.
36
VREF
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
Rev. C | Page 8 of 16
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