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ADV7125JSTZ240 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7125JSTZ240 CMOS, 330 MHz Triple 8-Bit High Speed Video DAC ADI
Analog Devices ADI
ADV7125JSTZ240 Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADV7125
5 V TIMING SPECIFICATIONS
VAA = 5 V ± 5%,1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,2 unless otherwise noted, TJ MAX = 110°C.
Table 3.
Parameter3
ANALOG OUTPUTS
Analog Output Delay
Analog Output Rise/Fall Time4
Analog Output Transition Time5
Analog Output Skew6
CLOCK CONTROL
CLOCK Frequency7
Data and Control Setup6
Data and Control Hold6
CLOCK Period
CLOCK Pulse Width High6
CLOCK Pulse Width Low6
CLOCK Pulse Width High6
CLOCK Pulse Width Low6
CLOCK Pulse Width High
CLOCK Pulse Width Low
Pipeline Delay6
PSAVE Up Time6
Symbol Min
t6
t7
t8
t9
fCLK
0.5
0.5
0.5
t1
0.5
t2
1.5
t3
4.17
t4
1.875
t5
1.875
t4
2.85
t5
2.85
t4
8.0
t5
8.0
tPD
1.0
t10
Typ Max
5.5
1.0
15
1
2
50
140
240
1.0 1.0
2
10
Unit
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock cycles
ns
Conditions
50 MHz grade
140 MHz grade
240 MHz grade
fCLK_MAX = 240 MHz
fCLK_MAX = 240 MHz
fCLK_MAX = 140 MHz
fCLK_MAX = 140 MHz
fCLK_MAX = 50 MHz
fCLK_MAX = 50 MHz
1 The maximum and minimum specifications are guaranteed over this range.
2 Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.
3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for both 5 V and 3.3 V supplies.
4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5 Measured from 50% point of full-scale transition to 2% of final value.
6 Guaranteed by characterization.
7 fCLK maximum specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
Rev. C | Page 5 of 16
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