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ADSP-BF542 View Datasheet(PDF) - Analog Devices

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Description
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ADSP-BF542
ADI
Analog Devices ADI
ADSP-BF542 Datasheet PDF : 100 Pages
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ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing
Table 34 and Figure 20 describe DDR SDRAM/mobile DDR
SDRAM write cycle timing.
Table 34. DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing
DDR SDRAM
Parameter
Min
Max
Switching Characteristics
tDQSS
Write CMD to First DQS0-1
0.75
1.25
tDS
DQ0-15/DQM0-1 Setup to DQS0-1
0.90
tDH
DQ0-15/DQM0-1 Hold to DQS0-1
0.90
tDSS
DQS0-1 Falling to DCK0-1 Rising (DQS0-1 Setup)
0.20
tDSH
DQS0-1 Falling from DCK0-1 Rising (DQS0-1 Hold) 0.20
tDQSH
DQS0-1 High Pulse Width
0.35
tDQSL
DQS0-1 Low Pulse Width
0.35
tWPRE
DQS0-1 Write Preamble
0.25
tWPST
DQS0-1 Write Postamble
0.40
0.60
tDOPW
DQ0-15 and DQM0-1 Output Pulse Width (for Each) 1.75
Mobile DDR SDRAM
Min
Max
0.75
1.25
0.90
0.90
0.20
0.20
0.40
0.60
0.40
0.60
0.25
0.40
0.60
1.75
Unit
tCK
ns
ns
tCK
tCK
tCK
tCK
tCK
tCK
ns
DCK0-1
DQS0-1
DQ0-15/DQM0-1
CONTROL
tDQSS
tDSH
tDSS
tWPRE
tDOPW
Dn
tDQSL
tDQSH
tWPST
Dn+1
Dn+2
Dn+3
tDS tDH
Write CMD
NOTE: CONTROL = DCS0-1, DCLKE, DRAS, DCAS, AND DWE.
Figure 20. DDR SDRAM /Mobile DDR SDRAM Controller Write Cycle Timing
Rev. C | Page 50 of 100 | February 2010
 

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