ADSP-BF531/ADSP-BF532/ADSP-BF533
plus the various output disable times as specified in the Timing
Specifications on Page 24 (for example tDSDAT for an SDRAM
write cycle as shown in SDRAM Interface Timing on Page 28).
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 44). VLOAD is 0.95 V for VDDEXT
(nominal) = 1.8 V or 1.5 V for VDDEXT (nominal) =
2.5 V/3.3 V. Figure 45 through Figure 56 on Page 48 show how
output rise time varies with capacitance. The delay and hold
specifications given should be derated by a factor derived from
these figures. The graphs in these figures may not be linear out
side the ranges shown.
TO
OUTPUT
PIN
50�
30pF
VLOAD
Figure 44. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
16
14
RISE TIME
12
10
FALL TIME
8
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 45. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver A at VDDEXT = 1.75 V
14
12
RISE TIME
10
8
FALL TIME
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 46. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver A at VDDEXT = 2.25 V
12
10
RISE TIME
8
FALL TIME
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 47. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver A at VDDEXT = 3.65 V
14
12
RISE TIME
10
8
FALL TIME
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 48. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver B at VDDEXT = 1.75 V
Rev. E | Page 46 of 60 | July 2007