ADSP-BF531 View Datasheet(PDF) - Analog Devices
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ADSP-BF531 Datasheet PDF : 60 Pages
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ADSP-BF531/ADSP-BF532/ADSP-BF533
150
VDDEXT = 3.65V
100
VDDEXT = 3.30V
VDDEXT = 2.95V
50
0
VOH
–50
VOL
–100
–150
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SOURCE VOLTAGE (V)
Figure 41. Drive Current D (VDDEXT = 3.3 V)
POWER DISSIPATION
Many operating conditions can affect power dissipation. System
designers should refer to Estimating Power for ADSP-BF531/
BF532/BF533 Blackfin Processors (EE-229) on the Analog
Devices website (www.analog.com)—use site search on
“EE-229.” This document provides detailed information for
optimizing your design for lowest power.
See the ADSP-BF533 Blackfin Processor Hardware Reference
Manual for definitions of the various operating modes and for
instructions on how to minimize system power.
TEST CONDITIONS
All timing parameters appearing in this data sheet were mea
sured under the conditions described in this section. Figure 42
shows the measurement point for ac measurements (except out
put enable/disable). The measurement point VMEAS is 0.95 V for
VDDEXT (nominal) = 1.8 V or 1.5 V for VDDEXT (nominal) = 2.5 V/
3.3 V.
INPUT
OR
VMEAS
OUTPUT
VMEAS
Figure 42. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
Output Enable Time Measurement
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving.
The output enable time tENA is the interval from the point when a
reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of
Figure 43.
The time tENA_MEASURED is the interval, from when the reference sig-
nal switches, to when the output voltage reaches VTRIP(high) or
VTRIP (low). For VDDEXT (nominal) = 1.8 V—VTRIP (high) is 1.3 V
and VTRIP (low) is 0.7 V. For VDDEXT (nominal) = 2.5 V/3.3 V—
VTRIP (high) is 2.0 V and VTRIP (low) is 1.0 V . Time tTRIP is the
interval from when the output starts driving to when the output
reaches the VTRIP (high) or VTRIP (low) trip voltage.
Time tENA is calculated as shown in the equation:
tENA = tENA_MEASURED – tTRIP
If multiple pins (such as the data bus) are enabled, the measure
ment value is that of the first pin to start driving.
Output Disable Time Measurement
Output pins are considered to be disabled when they stop driv
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time tDIS is the
difference between tDIS_MEASURED and tDECAY as shown on the left
side of Figure 42.
tDIS = tDIS_MEASURED – tDECAY
The time for the voltage on the bus to decay by ΔV is dependent
on the capacitive load CL and the load current II. This decay time
can be approximated by the equation:
tDECAY = (CLΔV) ⁄ IL
The time tDECAY is calculated with test loads CL and IL, and with
ΔV equal to 0.1 V for VDDEXT (nominal) = 1.8 V or 0.5 V for
VDDEXT (nominal) = 2.5 V/3.3 V.
The time tDIS_MEASURED is the interval from when the reference
signal switches, to when the output voltage decays ΔV from the
measured output high or output low voltage.
tDIS
VOH
(MEASURED)
VOL
(MEASURED)
REFERENCE
SIGNAL
tDIS_MEASURED
tENA
VOH (MEASURED) � �V
VOL (MEASURED) + �V
tDECAY
tENA_MEASURED
VOH(MEASURED)
VTRIP(HIGH)
VTRIP(LOW)
VOL(MEASURED)
tTRIP
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE
Figure 43. Output Enable/Disable
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ΔV
to be the difference between the ADSP-BF531/ADSP-BF532/
ADSP-BF533 processor’s output voltage and the input thresh-
old for the device requiring the hold time. CLis the total bus
capacitance (per data line), and IL is the total leakage or
three-state current (per data line). The hold time will be tDECAY
Rev. E | Page 45 of 60 | July 2007
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