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ADSP-BF531 View Datasheet(PDF) - Analog Devices

Part Name
Description
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ADSP-BF531
ADI
Analog Devices ADI
ADSP-BF531 Datasheet PDF : 60 Pages
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ADSP-BF531/ADSP-BF532/ADSP-BF533
Parallel Peripheral Interface Timing
Table 21 and Figure 16 through Figure 21 on Page 33 describe
parallel peripheral interface operations.
Table 21. Parallel Peripheral Interface Timing
VDDEXT = 1.8 V
LQFP/PBGA Packages
Parameter
Min
Max
Timing Requirements
tPCLKW PPI_CLK Width
8.0
tPCLK PPI_CLK Period1
20.0
tSFSPE External Frame Sync Setup Before PPI_CLK Edge
6.0
(Nonsampling Edge for Rx, Sampling Edge for Tx)
tHFSPE External Frame Sync Hold After PPI_CLK
1.02
2.03
tSDRPE Receive Data Setup Before PPI_CLK
3.5
tHDRPE Receive Data Hold After PPI_CLK
1.5
Switching Characteristics—GP Output and Frame Capture Modes
tDFSPE
tHOFSPE
tDDTPE
tHDTPE
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
11.0
1.7
11.0
1.8
1 PPI_CLK frequency cannot exceed fSCLK/2
2 Applies when PPI_CONTROL Bit 8 is cleared. See Figure 17 on Page 31 and Figure 20 on Page 32.
3 Applies when PPI_CONTROL Bit 8 is set. See Figure 18 on Page 31 and Figure 21 on Page 33.
VDDEXT = 1.8 V
MBGA Package
Min Max
8.0
20.0
6.0
1.02
2.03
3.5
1.5
8.0
1.7
9.0
1.8
VDDEXT = 2.5 V/3.3 V
All Packages
Min Max
Unit
6.0
ns
15.0
ns
4.02
ns
6.03
ns
1.02
ns
2.03
3.5
ns
1.5
ns
8.0
ns
1.7
ns
9.0
ns
1.8
ns
POLC = 0
PPI_CLK
PPI_CLK
POLC = 1
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
PPI_DATA
FRAME
SYNC IS
DRIVEN
OUT
DATA0
IS
SAMPLED
tDFSPE
tHOFSPE
tSDRPE
tHDRPE
Figure 16. PPI GP Rx Mode with Internal Frame Sync Timing
Rev. E | Page 30 of 60 | July 2007
 

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