ADSP-BF531 View Datasheet(PDF) - Analog Devices
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Description
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ADSP-BF531 Datasheet PDF : 60 Pages
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ADSP-BF531/ADSP-BF532/ADSP-BF533
External Port Bus Request and Grant Cycle Timing
Table 20 and Figure 15 describe external port bus request and
bus grant operations.
Table 20. External Port Bus Request and Grant Cycle Timing
Parameter
Timing Requirements
tBS BR Asserted to CLKOUT High Setup
tBH CLKOUT High to BR Deasserted Hold Time
Switching Characteristics
tSD CLKOUT Low to AMSx, Address, and ARE/AWE Disable
tSE CLKOUT Low to AMSx, Address, and ARE/AWE Enable
tDBG CLKOUT High to BG High Setup
tEBG CLKOUT High to BG Deasserted Hold Time
tDBH CLKOUT High to BGH High Setup
tEBH CLKOUT High to BGH Deasserted Hold Time
VDDEXT = 1.8 V
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
LQFP/PBGA Packages MBGA Package All Packages
Min
Max
Min Max Min Max
Unit
4.6
4.6
4.6
ns
1.0
1.0
0.0
ns
4.5
4.5
4.5
ns
4.5
4.5
4.5
ns
6.0
4.6
3.6
ns
6.0
4.6
3.6
ns
6.0
4.6
3.6
ns
6.0
4.6
3.6
ns
CLKOUT
tB S
BR
AMSx
ADDR19-1
ABE1-0
AWE
ARE
BG
BGH
tBH
tSD
tSD
tSD
tDBG
tDBH
Figure 15. External Port Bus Request and Grant Cycle Timing
tSE
tSE
tSE
tEBG
tEBH
Rev. E | Page 29 of 60 | July 2007
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