ADSP-BF531/ADSP-BF532/ADSP-BF533
Asynchronous Memory Write Cycle Timing
Table 18. Asynchronous Memory Write Cycle Timing
Parameter
Timing Requirements
tSARDY
ARDY Setup Before CLKOUT
tHARDY
ARDY Hold After CLKOUT
Switching Characteristics
tDDAT
DATA15–0 Disable After CLKOUT
tENDAT
DATA15–0 Enable After CLKOUT
tDO
Output Delay After CLKOUT1
tHO
Output Hold After CLKOUT 1
1 Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
SETUP
2 CYCLES
PROGRAMMED WRITE
ACCESS 2 CYCLES
ACCESS
EXTENDED
1 CYCLE
HOLD
1 CYCLE
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Min Max Min Max
Unit
4.0
4.0
ns
1.0
0.0
ns
6.0
6.0
ns
1.0
1.0
ns
6.0
6.0
ns
1.0
0.8
ns
CLKOUT
t DO
tHO
AMSx
ABE1–0
ADDR19–1
AWE
ARDY
DATA15–0
ABE, ADDRESS
tDO
t SARDY
tHO
t HARDY
t ENDAT
WRITE DATA
tSARDY
tDDAT
Figure 13. Asynchronous Memory Write Cycle Timing
Rev. E | Page 27 of 60 | July 2007