ADSP-BF531/ADSP-BF532/ADSP-BF533
PIN DESCRIPTIONS
ADSP-BF531/ADSP-BF532/ADSP-BF533 processor pin defini
tions are listed in Table 9.
All pins are three-stated during and immediately after reset,
except the memory interface, asynchronous memory control,
and synchronous memory control pins, which are driven high.
If BR is active, then the memory pins are also three-stated. All
unused I/O pins have their input buffers disabled with the
exception of the pins that need pull-ups or pull-downs as noted
in the table footnotes.
In order to maintain maximum functionality and reduce pack
age size and pin count, some pins have dual, multiplexed
functionality. In cases where pin functionality is reconfigurable,
the default state is shown in plain text, while alternate function
ality is shown in italics.
Table 9. Pin Descriptions
Pin Name
Type Function
Memory Interface
ADDR19–1
O Address Bus for Async/Sync Access
DATA15–0
I/O Data Bus for Async/Sync Access
ABE1–0/SDQM1–0
O Byte Enables/Data Masks for Async/Sync Access
BR
I Bus Request (This pin should be pulled HIGH if not used.)
BG
O Bus Grant
BGH
O Bus Grant Hang
Asynchronous Memory Control
AMS3–0
O Bank Select
ARDY
I Hardware Ready Control (This pin should be pulled HIGH if not used.)
AOE
O Output Enable
ARE
O Read Enable
AWE
O Write Enable
Synchronous Memory Control
SRAS
O Row Address Strobe
SCAS
O Column Address Strobe
SWE
O Write Enable
SCKE
O Clock Enable
CLKOUT
O Clock Output
SA10
O A10 Pin
SMS
O Bank Select
Timers
TMR0
I/O Timer 0
TMR1/PPI_FS1
I/O Timer 1/PPI Frame Sync1
TMR2/PPI_FS2
I/O Timer 2/PPI Frame Sync2
PPI Port
PPI3–0
I/O PPI3–0
PPI_CLK/TMRCLK
I PPI Clock/External Timer Reference
Driver
Type1
A
A
A
A
A
A
A
A
A
A
A
A
A
B
A
A
C
C
C
C
Rev. E | Page 18 of 60 | July 2007