|ADS7870EA||12-BIT, 52-kSPS, DATA ACQUISITION SYSTEM WITH ANALOG-TO-DIGITAL CONVERTER, MUX, PGA, AND REFERENCE|
|ADS7870EA Datasheet PDF : 46 Pages |
SBAS124C − DECEMBER 1999 − REVISED DECEMBER 2005
In this mode, the serial interface configures itself to clockout a conversion result as soon as a conversion is
started. This is useful since a read instruction is not required so eight SCLK cycles are saved. This mode
operates like an implied sixteen bit read instruction byte for ADDR = 1 was sent to the ADS7870 after starting
It is not necessary to wait for the end of the conversion to start clocking out conversion results. The last
completed conversion at the sampling edge of SCLK is read back (whether a conversion is in progress or not).
This mode is similar to Mode 1 except that the conversion result is provided LS byte first (equivalent to a sixteen
bit read from ADDR = 0).
Figure 38 and Figure 39 show timing examples of an automatic read back operation using mode 2. In Figure 38,
the result of the previous conversion is retrieved. This example is for LSB first, CCLK divider = 2, and SCLK
active on the rising edge. The data may be read back immediately after the start conversion instruction. It is
not necessary to wait for the conversion to actually start (or finish).
First output bit loaded in the output register
The remaining output bits loaded in the output register
DODUIÓÓÓNT ÓÓÓÓÓMÓÓ0 ÓÓM1 ÓÓM2 ÓÓM3ÓÓG0ÓÓGÓÓ1 GÓÓ2 ÓÓÓÓÓ1 OÓÓÓVR ÓÓÓ0 ÓÓÓ0 ÓÓÓ0ÓÓÓBÓÓÓ0 BÓÓÓ1 BÓÓÓ2 ÓÓÓB3 ÓÓÓB4ÓÓÓB5ÓÓÓB6ÓÓÓBÓÓÓ7 ÓÓÓB8 ÓÓÓB9 ÓÓÓB10ÓÓÓB11ÓÓÓ
Figure 38. Timing Diagram for Automatic Read Back of Previous Conversion Result Using Mode 2
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