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ADS7870EA View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
ADS7870EA 12-BIT, 52-kSPS, DATA ACQUISITION SYSTEM WITH ANALOG-TO-DIGITAL CONVERTER, MUX, PGA, AND REFERENCE TI
Texas Instruments TI
ADS7870EA Datasheet PDF : 46 Pages
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ADS7870
www.ti.com
SBAS124C − DECEMBER 1999 − REVISED DECEMBER 2005
Read Operation
A read operation is similar to a write operation except that data flow (after the instruction byte) is from the
ADS7870 to the host controller. After the instruction byte has been latched (on the eighth active edge of SCLK),
the DOUT pin (and the DIN pin if in two-wire mode) begins driving data on the next nonactive edge of SCLK.
This allows the host controller to have valid data on the next active edge of SCLK.
The data on DOUT (or DIN) transitions on the nonactive edges of SCLK. The DIN pin (two-wire mode) ceases
driving data (return to high impedance) on the nonactive edge of SCLK following the eighth (or sixteenth) active
edge of the read data. DOUT is only high impedance when CS is not asserted. With CS high (1), DOUT (or
DIN) is forced to high impedance mode. In general, the ADS7870 is insensitive to the idle state of the clock
except that the state of SCLK may determine if DIN is driving data or not.
Upon completion of the read operation, the ADS7870 is ready to receive the next instruction byte. Read
operations reflect the state of the ADS7870 on the first active edge of SCLK of the data byte transferred.
Figure 18 shows an example of an eight-bit read operation with LSB first and SCLK active on the rising edge.
The double rising arrows indicate when the instruction is latched.
SCLK
DIN
DOUT
ÓÓÓÓAÓÓ0 ÓÓA1ÓÓAÓÓ2 ÓÓA3 ÓÓA4ÓÓÓÓ0 ÓÓ1 ÓÓÓÓÓÓ0 ÓÓD0 ÓÓD1ÓÓÓÓD2 ÓÓD3ÓÓDÓÓ4 ÓÓD5ÓÓDÓÓ6 ÓÓD7 ÓÓ
CS
Figure 18. Timing Diagram for an 8-Bit Read Operation
Figure 19 provides an example of a 16-bit read operation from an odd address with LSB first and SCLK active
on the rising edge. The address (ADDR) for the second byte is decremented by one since the ADDR in the
instruction byte is odd. For an even ADDR, the address for the second byte would be incremented by one.
SCLK
Ó ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ DIN
1 A1 A2 A3 A4 1 1 0
ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ DOUT
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Data from ADDR
Data from ADDR−1
CS
Figure 19. Timing Diagram for a 16-Bit Read Operation to an Odd Address
19
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