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ADS7870EA View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
ADS7870EA 12-BIT, 52-kSPS, DATA ACQUISITION SYSTEM WITH ANALOG-TO-DIGITAL CONVERTER, MUX, PGA, AND REFERENCE TI
Texas Instruments TI
ADS7870EA Datasheet PDF : 46 Pages
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ADS7870
SBAS124C − DECEMBER 1999 − REVISED DECEMBER 2005
Conversion Cycle
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A conversion cycle requires 48 DCLKs, where DCLK = CCLK/DF, the divided−down clock. Operation of the
PGA requires 36 DCLKs: capture the input signal, auto-zero the PGA, level-shift and amplify the input signal.
The period of this cycle makes certain the settling time is sufficient for gain = 20 and (source impedance of 2
kor less) even if the gain is less than 20. The SAR converter takes the last 12 DCLKs.
For maximum sampling rate the input command and output data must be communicated during this cycle,
although this is not recommended for best performance.
During the conversion cycle the internal capacitive load at the selected MUX input changes between 6 pF and
9.7 pF. When the ADS7870 is not converting, the MUX inputs have a nominal 4-pF load capacitance.
The source impedance of the input causes the voltage to vary on the DCLK transitions as the internal capacitors
are switched in and out. A 10-nF to 100-nF capacitor across the differential inputs helps filter these glitches
and act as an antialias filter in combination with the source impedance. Source impedance greater than 2 k
requires longer settling times and so CCLK should be reduced accordingly.
For minimum power dissipation, the bias needed for each function is turned on, allowed to settle, and run only
for the duration required for each conversion. Low rate data logging applications can capitalize on this by
utilizing the internal oscillator as needed rather than running a slow system clock.
Starting an A/D Conversion Cycle
There are four ways to cause the ADS7870 to perform a conversion:
1.
2.
Send a direct mode instruction.
Write to register 4 with the CNV bit = 1
} The next conversion queues up, waiting for the
current conversion to complete
3. Write to register 5 with the CNV bit = 1
4. Assert the CONVERT pin (logic high) — A new conversion cycle starts at the second active
edge of CCLK.
Serial Interface
The ADS7870 communicates with microprocessors and other external circuitry through a digital serial port
interface. It is compatible with a wide variety of popular microcontrollers and digital signal processors (DSP).
These include TI’s TMS320, MSC1210, and MSP430 product families. Other vendors products such as
Motorola 68HC11, Intel 80C51, and MicroChip PIC Series are also supported.
The serial interface consists of four primary pins, SCLK (serial bit clock), DIN (serial data input), DOUT (serial
data output) and CS (chip select). SCLK synchronizes the data transfer with each bit being transmitted on the
falling or rising SCLK edge as determined by the RISE/FALL pin. SDIN may also be used as a serial data output
line.
Additional pins expand the versatility of the basic serial interface and allow it to be used with different
microcontrollers. The BUSY pin indicates when a conversion is in progress and may be used to generate
interrupts for the microcontroller. The CONVERT pin can be used as a hardware-based method of causing the
ADS7870 to start a conversion cycle. The RESET pin can be toggled in order to reset the ADS7870 to the
power-on state.
Communication through the serial interface is dependent on the microcontroller providing an instruction byte
followed by either additional data (for a write operation) or just additional SCLKs to allow the ADS7870 to provide
data (for a read operation). Special operating modes for reducing the instruction byte overhead for retrieving
conversion results are available.
Reset of device (RESET), start of conversion (CONVERT), and oscillator enable (OSC ENABLE) can be done
by signals to external pins or entries to internal registers. The actual execution of each of these commands is
a logical OR function; either pin or register signal TRUE causes the function to execute. The CONVERT pin
signal is an edge-triggered event, with a hold time of two CCLK periods for debounce.
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