ADP5052 View Datasheet(PDF) - Analog Devices

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Description

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ADP5052

5-Channel Integrated Power Solution with Quad Buck Regulators and 200 mA LDO Regulator

Analog Devices 

Data Sheet

ADP5052

SELECTING THE OUTPUT CAPACITOR

The output capacitor must meet the output voltage ripple and

load transient requirements. To meet the output voltage ripple

requirement, use the following equations to calculate the ESR

and capacitance:

COUT _ RIPPLE =

∆I L

8 × fSW × ∆VOUT _ RIPPLE

RESR =

∆VOUT _ RIPPLE

∆I L

The calculated capacitance, C , OUT_RIPPLE is 20.8 µF, and the

calculated RESR is 10 mΩ.

To meet the ±5% overshoot and undershoot requirements,

use the following equations to calculate the capacitance:

( ) COUT _UV

=

2×

KUV × ∆ISTEP 2 × L

VIN − VOUT × ∆VOUT _UV

( ) COUT _OV =

KOV × ∆ISTEP 2 × L

VOUT + ∆VOUT_OV 2 − VOUT 2

For estimation purposes, use KOV = KUV = 2; therefore,

COUT_OV = 117 µF and COUT_UV = 13.3 µF.

The ESR of the output capacitor must be less than 13.3 mΩ,

and the output capacitance must be greater than 117 µF. It is

recommended that three ceramic capacitors be used (47 µF,

X5R, 6.3 V), such as the GRM21BR60J476ME15 from Murata

with an ESR of 2 mΩ.

SELECTING THE LOW-SIDE MOSFET

A low RDSON N-channel MOSFET must be selected for high

efficiency solutions. The MOSFET breakdown voltage (VDS)

must be greater than 1.2 × VIN, and the drain current must

be greater than 1.2 × I . LIMIT_MAX

It is recommended that a 20 V, dual N-channel MOSFET—such

as the Si7232DN from Vishay—be used for both Channel 1 and

Channel 2. The RDSON of the Si7232DN at 4.5 V driver voltage is

16.4 mΩ, and the total gate charge is 12 nC.

DESIGNING THE COMPENSATION NETWORK

For better load transient and stability performance, set the cross

frequency, fC, to fSW/10. In this example, fSW is set to 600 kHz;

therefore, fC is set to 60 kHz.

For the 1.2 V output rail, the 47 µF ceramic output capacitor has

a derated value of 40 µF.

RC

=

2

×

π ×1.2

0.8 V

V

×

× 3 × 40 µF × 60

470 µS ×10A/V

kHz

= 14.4 k Ω

( ) CC =

0.3 Ω + 0.001 Ω × 3 × 40 µF = 2.51 nF

14.4 k Ω

Choose standard components: RC = 15 kΩ and CC = 2.7 nF.

CCP is optional.

Figure 50 shows the Bode plot for the 1.2 V output rail.

The cross frequency is 62 kHz, and the phase margin is 58°.

Figure 51 shows the load transient waveform.

100

120

80

90

60

60

40

30

20

0

0

–30

–20

–60

–40

–90

–60

–120

–80

CROSS FREQUENCY: 62kHz

–100 PHASE MARGIN: 58°

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 50. Bode Plot for 1.2 V Output

–150

–180

VOUT

1

IOUT

4

CH1 50.0mV BW

M200µs

CH4 2.00A Ω BW

A CH4 2.32A

Figure 51. 0.8 A to 3.2 A Load Transient for 1.2 V Output

SELECTING THE SOFT START TIME

The soft start feature allows the output voltage to ramp up in a

controlled manner, eliminating output voltage overshoot during

soft start and limiting the inrush current.

The SS12 pin can be used to program a soft start time of 2 ms,

4 ms, or 8 ms and can also be used to configure parallel opera-

tion of Channel 1 and Channel 2. For more information, see the

Soft Start section and Table 8.

SELECTING THE INPUT CAPACITOR

For the input capacitor, select a ceramic capacitor with a mini-

mum value of 10 µF; place the input capacitor close to the PVIN1

pin. In this example, one 10 µF, X5R, 25 V ceramic capacitor is

recommended.

CCP =

0.001 Ω × 3 ×40 µF = 8.3 pF

14.4 k Ω

Rev. 0 | Page 29 of 40

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