ADP5050 View Datasheet(PDF) - Analog Devices

Part Name

Description

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ADP5050

5-Channel Integrated Power Solution with Quad Buck Regulators and 200 mA LDO Regulator

Analog Devices 

Data Sheet

C1

1.0µF

12V

VREG

VDD

C0

1.0µF

PVIN1

C2

10µFCOMP1

2.7nF

10kΩ

EN1

VREG SS12

PVIN2

C5

10µF

COMP2

2.7nF

10kΩ

EN2

PVIN3

C8

10µF COMP3

2.7nF

6.81kΩ

EN3

VREG SS34

PVIN4

C11

10µF

COMP4

2.7nF

6.81kΩ

EN4

EN5

OPTIONAL

I2C INTERFACE

VDDIO

SCL

SDA

ADP5050

ADP5050

INT VREG

100mA

OSCILLATOR

CHANNEL 1

BUCK REGULATOR

(1.2A/2.5A/4A)

5V REG

CHANNEL 2

BUCK REGULATOR

(1.2A/2.5A/4A)

5V REG

CHANNEL 3

BUCK REGULATOR

(1.2A)

VREG

SYNC/MODE

RT 31.6kΩ

FB1

10kΩ

BST1

SW1

C3

0.1µF

DL1

Q1

PGND 22kΩ

DL2 22kΩ

4.99kΩ

L1

1.5µH

VOUT1

C4

47µF

Si7232DN

(16.4mΩ)

SW2

BST2

FB2

Q2

L2

C6

0.1µF

2.2µH

21.5kΩ

10.2kΩ

BST3

SW3

FB3

C9

0.1µF

L3

6.8µH

8.87kΩ

PGND3

10.2kΩ

VOUT2

C7

47µF

VOUT3

C10

22µF

CHANNEL 4

BUCK REGULATOR

(1.2A)

CHANNEL 5

200mA LDO

REGULATOR

I2C

ALERT

BST4

SW4

FB4

C12

0.1µF

L4

10µH

31.6kΩ

PGND4

10.2kΩ

PVIN5

VOUT5

FB5

14kΩ

PWRGD

10kΩ

INT

VOUT4

C13

22µF

VOUT5

C15

1µF

1.2V/4A

C16

47µF

2.5V/4A

C17

47µF

1.5V/1.2A

DDR

TERM. LDO

3.3V/1.2A

C14

1µF

1.2V/100mA

VCORE

FPGA

AUXILIARY

VOLTAGE

I/O BANK 0

I/O BANK 1

I/O BANK 2

I/O BANK 3 MGTs

DDR

MEMORY

FLASH

MEMORY

EXPOSED PAD

Figure 67. Typical FPGA Application, 600 kHz Switching Frequency, Adjustable Output Model

Rev. B | Page 39 of 57

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