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ADP3339AKC-3-RL7 View Datasheet(PDF) - Analog Devices

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ADP3339AKC-3-RL7 Datasheet PDF : 15 Pages
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THEORY OF OPERATION
The ADP3339 anyCAP LDO uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider, consisting of R1 and R2, which is
varied to provide the available output voltage option. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that equilibrium
produces a large, temperature-proportional input offset voltage
that is repeatable and very well controlled. The temperature-
proportional offset voltage is combined with the complemen-
tary diode voltage to form a virtual band gap voltage that is
implicit in the network, although it never appears explicitly in
the circuit. Ultimately, this patented design makes it possible to
control the loop with only one amplifier. This technique also
improves the noise characteristics of the amplifier by providing
more flexibility on the trade-off of noise sources that leads to a
low noise design.
The R1, R2 divider is chosen in the same ratio as the band gap
voltage to the output voltage. Although the R1, R2 resistor
divider is loaded by diode D1 and a second divider consisting of
R3 and R4, the values can be chosen to produce a temperature-
stable output. This unique arrangement specifically corrects for
the loading of the divider, thus avoiding the error resulting from
base current loading in conventional circuits.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole-splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitance.
ADP3339
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to
stabilize due to the uncertainty of load capacitance and resis-
tance. Moreover, the ESR value required to keep conventional
LDOs stable changes depending on load and temperature.
These ESR limitations make designing with LDOs more
difficult because of their unclear specifications and extreme
variations over temperature.
With the ADP3339 anyCAP LDO, this is no longer true. It can
be used with virtually any good quality capacitor, with no
constraint on the minimum ESR. This innovative design allows
the circuit to be stable with just a small 1 µF capacitor on the
output. Additional advantages of the pole-splitting scheme
include superior line noise rejection and very high regulator
gain, which lead to excellent line and load regulation. An
impressive ±1.5 accuracy is guaranteed over line, load, and
temperature.
Additional features of the circuit include current limit and
thermal shutdown.
VIN
C1
1µF
IN
OUT
GND
ADP3339
VOUT
C2
1µF
Figure 20. Typical Application Circuit
INPUT
OUTPUT
Q1
COMPENSATION
CAPACITOR
ATTENUATION
(VBANDGAP/VOUT)
NONINVERTING
WIDEBAND
DRIVER
PTAT
R3 D1
gm
VOS
PTAT
R4 CURRENT
ADP3339
R1
(a) CLOAD
RLOAD
R2
GND
Figure 21. Functional Block Diagram
Rev. A | Page 9 of 12
 

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