|ADP122AUJZ-3.3-R7||5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator|
|ADP122AUJZ-3.3-R7 Datasheet PDF : 20 Pages |
POWER SUPPLY REJECTION RATIO
(VIN = VOUT + 0.5 V)
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.2 V
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.8 V
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 2.5 V
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 3.3 V
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 4.2 V
10 kHz, VOUT = 3.3 V
10 kHz, VOUT = 2.5 V
10 kHz, VOUT = 1.8 V
100 kHz, VOUT = 3.3 V
100 kHz, VOUT = 2.5 V
100 kHz, VOUT = 1.8 V
Min Typ Max Unit
1 The current from the external resistor divider network in the case of adjustable voltage output (as with the ADP123) should be subtracted from the ground current measured.
2 Accuracy when VOUT is connected directly to ADJ. When VOUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances of
the resistors used.
3 Based on an endpoint calculation using 1 mA and 300 mA loads.
4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages
greater than 2.3 V.
5 Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.
6 Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.3 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.3V, or 2.97 V.
Minimum Input and Output
TA = −40°C to +125°C
TA = −40°C to +125°C
1 The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. 0 | Page 4 of 20
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