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ADP121CB-2.5-EVALZ View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADP121CB-2.5-EVALZ 150 mA, Low Quiescent Current, CMOS Linear Regulator ADI
Analog Devices ADI
ADP121CB-2.5-EVALZ Datasheet PDF : 20 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
Data Sheet
Equation 1 can be used to determine the worst-case capacitance
accounting for capacitor variation over temperature, compo-
nent tolerance, and voltage.
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
(1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, TEMPCO over −40°C to +85°C is assumed to
be 15% for an X5R dielectric. TOL is assumed to be 10%, and
CBIAS is 0.94 μF at 1.8 V from the graph in Figure 30.
Substituting these values in Equation 1 yields
CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP121, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors are evaluated for each application.
UNDERVOLTAGE LOCKOUT
The ADP121 has an internal undervoltage lockout circuit that
disables all inputs and the output when the input voltage is less
than approximately 2.2 V. This ensures that the inputs of the
ADP121 and the output behave in a predictable manner during
power-up.
ENABLE FEATURE
The ADP121 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. Figure 31 shows a
rising voltage on EN crossing the active threshold, and then
VOUT turns on. When a falling voltage on EN crosses the
inactive threshold, VOUT turns off.
VIN = 5V
VOUT = 1.8V
CIN = COUT = 1µF
ILOAD = 100mA
VOUT
EN
ADP121
As shown in Figure 31, the EN pin has built in hysteresis. This
prevents on/off oscillations that may occur due to noise on the
EN pin as it passes through the threshold points.
The active/inactive thresholds of the EN pin are derived from
the VIN voltage. Therefore, these thresholds vary with changing
input voltage. Figure 32 shows typical EN active/inactive
thresholds when the input voltage varies from 2.3 V to 5.5 V.
1.10
1.05
1.00
EN ACTIVE
0.95
0.90
0.85
EN INACTIVE
0.80
0.75
0.70
2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50
VIN (V)
Figure 32. Typical EN Pin Thresholds vs. Input Voltage
The ADP121 utilizes an internal soft start to limit the inrush
current when the output is enabled. The start-up time for the
1.8 V option is approximately 120 µs from the time the EN
active threshold is crossed to when the output reaches 90% of its
final value. The start-up time is somewhat dependant on the
output voltage setting and increases slightly as the output
voltage increases.
6
EN
5
4
3
3.3V
2
1.8V
1
1.2V
0
0 20 40 60 80 100 120 140 160 180 200
TIME (µs)
Figure 33. Typical Start-Up Time
40ms/DIV
Figure 31. ADP121 Typical EN Pin Operation
Rev. G | Page 13 of 20
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