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ADP121CB-2.5-EVALZ View Datasheet(PDF) - Analog Devices

Part NameADP121CB-2.5-EVALZ ADI
Analog Devices ADI
Description150 mA, Low Quiescent Current, CMOS Linear Regulator

ADP121CB-2.5-EVALZ Datasheet PDF : 20 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
Data Sheet
Equation 1 can be used to determine the worst-case capacitance
accounting for capacitor variation over temperature, compo-
nent tolerance, and voltage.
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, TEMPCO over −40°C to +85°C is assumed to
be 15% for an X5R dielectric. TOL is assumed to be 10%, and
CBIAS is 0.94 μF at 1.8 V from the graph in Figure 30.
Substituting these values in Equation 1 yields
CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP121, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors are evaluated for each application.
The ADP121 has an internal undervoltage lockout circuit that
disables all inputs and the output when the input voltage is less
than approximately 2.2 V. This ensures that the inputs of the
ADP121 and the output behave in a predictable manner during
The ADP121 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. Figure 31 shows a
rising voltage on EN crossing the active threshold, and then
VOUT turns on. When a falling voltage on EN crosses the
inactive threshold, VOUT turns off.
VIN = 5V
VOUT = 1.8V
CIN = COUT = 1µF
ILOAD = 100mA
As shown in Figure 31, the EN pin has built in hysteresis. This
prevents on/off oscillations that may occur due to noise on the
EN pin as it passes through the threshold points.
The active/inactive thresholds of the EN pin are derived from
the VIN voltage. Therefore, these thresholds vary with changing
input voltage. Figure 32 shows typical EN active/inactive
thresholds when the input voltage varies from 2.3 V to 5.5 V.
2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50
Figure 32. Typical EN Pin Thresholds vs. Input Voltage
The ADP121 utilizes an internal soft start to limit the inrush
current when the output is enabled. The start-up time for the
1.8 V option is approximately 120 µs from the time the EN
active threshold is crossed to when the output reaches 90% of its
final value. The start-up time is somewhat dependant on the
output voltage setting and increases slightly as the output
voltage increases.
0 20 40 60 80 100 120 140 160 180 200
TIME (µs)
Figure 33. Typical Start-Up Time
Figure 31. ADP121 Typical EN Pin Operation
Rev. G | Page 13 of 20
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The ADP121 is a quiescent current, low dropout, linear regulator that operates from 2.3 V to 5.5 V and provides up to 150 mA of output current. The low 135 mV dropout voltage at 150 mA load improves efficiency and allows operation over a wide input voltage range. The low 30 μA of quiescent current at full load makes the ADP121 ideal for battery-operated portable equipment.
The ADP121 is available in output voltages ranging from 1.2 V to 3.3 V. The parts are optimized for stable operation with small 1 μF ceramic output capacitors. The ADP121 delivers good transient performance with minimal board area.
Short-circuit protection and thermal overload protection circuits prevent damage in adverse conditions. The ADP121 is available in a tiny 5-lead TSOT and 4-ball 0.4 mm pitch halide-free WLCSP packages and utilizes the smallest footprint solution to meet a variety of portable applications.

  Input voltage range: 2.3 V to 5.5 V
  Output voltage range: 1.2 V to 3.3 V
  Output current: 150 mA
  Low quiescent current
     IGND = 11 μA with 0 μA load
     IGND = 30 μA with 150 mA load
  Low shutdown current: <1 μA
  Low dropout voltage
     90 mV @ 150 mA load
  High PSRR
     70 dB @ 1 kHz at VOUT = 1.2 V
     70 dB @ 10 kHz at VOUT = 1.2 V
  Low noise: 40 μV rms at VOUT = 1.2 V
  No noise bypass capacitor required
  Output voltage accuracy: ±1%
  Stable with a small 1 μF ceramic output capacitor
  Current limit and thermal overload protection
  Logic controlled enable
  5-lead TSOT package
  4-ball 0.4 mm pitch WLCSP
  Mobile phones
  Digital cameras and audio devices
  Portable and battery-powered equipment
  Post dc-to-dc regulation
  Post regulation

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