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ADP1046ADC1-EVALZ View Datasheet(PDF) - Analog Devices

Part Name
Description
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ADP1046ADC1-EVALZ Datasheet PDF : 88 Pages
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Data Sheet
Parameter
Symbol Test Conditions/Comments
Min
Typ
Measurement Accuracy
Factory trimmed at 1 V
10 mV to 160 mV
−0.5
−8
0% to 100% of usable input voltage range −3.0
−42
Temperature Readings Using
Internal Linearization Scheme
RTD source set to 46 µA (Register 0x11 set to
0xE6); NTC R0 = 100 kΩ, 1%; beta = 4250, 1%;
REXT = 16.5 kΩ, 1%
25°C to 100°C
100°C to 125°C
OTP
Threshold Accuracy
T = 85°C with 100 kΩ||16.5 kΩ
−0.9
−14.4
T = 100°C with 100 kΩ||16.5 kΩ
−0.5
−8
Comparator Speed
10.5
OTP Threshold Hysteresis
16
PGOOD1, PGOOD2, SHAREo PINS
Open-drain outputs
Output Low Voltage
PSON, SHAREi PINS
VOL
Digital inputs
Input Low Voltage
VIL
Input High Voltage
VIH
Leakage Current
VDD − 0.8
FLAGIN PIN
Digital input
Input Low Voltage
Input High Voltage
Propagation Delay
VIL
VIH
VDD − 0.8
Does not include debounce time (Register
200
0x0A[3] = 1); flag action set to disable PSU
Leakage Current
GATE PIN
Output Low Voltage
Output High Voltage
SDA/SCL PINS
Input Low Voltage
Input High Voltage
Output Low Voltage
Leakage Current
VOL
VOH
VDD = 3.3 V
VIL
VIH
VOL
VDD − 0.4
VDD − 0.8
SERIAL BUS TIMING
See Figure 2
Clock Operating Frequency
10
100
Bus-Free Time
Start Hold Time
tBUF
tHD;STA
Between stop and start conditions
1.3
Hold time after (repeated) start condition; 0.6
after this period, the first clock is generated
Start Setup Time
Stop Setup Time
SDA Setup Time
SDA Hold Time
tSU;STA
Repeated start condition setup time
0.6
tSU;STO
0.6
tSU;DAT
100
tHD;DAT
For readback
125
For write
300
SCL Low Timeout
tTIMEOUT
25
SCL Low Period
tLOW
1.3
SCL High Period
tHIGH
0.6
Clock Low Extend Time
tLO;SEXT
SCL, SDA Fall Time
tF
20
SCL, SDA Rise Time
tR
20
Rev. 0 | Page 7 of 88
ADP1046A
Max
Unit
+0.5
% FSR
+8
mV
+3.0
% FSR
+42
mV
7
5
+0.25
+4
+1.1
+17.6
0.4
0.8
1.0
0.4
1.0
0.4
0.8
0.4
1.0
400
35
25
300
300
°C
°C
% FSR
mV
% FSR
mV
ms
mV
V
V
V
µA
V
V
ns
µA
V
V
V
V
V
µA
kHz
µs
µs
µs
µs
ns
ns
ns
ms
µs
µs
ms
ns
ns
 

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