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ADP1046ADC1-EVALZ View Datasheet(PDF) - Analog Devices

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ADP1046ADC1-EVALZ Datasheet PDF : 88 Pages
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Data Sheet
CURRENT SHARING
The ADP1046A supports both analog current sharing and
digital current sharing. The ADP1046A uses the CS2 current
information for current sharing (this setting is programmed
in Register 0x29[3]).
Analog Current Sharing
Analog current sharing uses the internal current sensing
circuitry to provide a current reading to an external current
error amplifier. Therefore, an additional differential current
amplifier is not necessary.
The current reading from CS2 can be output to the SHAREo
pin in the form of a digital bit stream, which is the output of the
current sense ADC (see Figure 33). The bit stream from the Σ-Δ
ADC is proportional to the current delivered by this unit to the
load. By filtering this digital bit stream using an external RC filter,
the current information is turned into an analog voltage that is
proportional to the current delivered by this unit to the load. This
voltage can be compared to the share bus voltage. If the unit is not
supplying enough current, an error signal can be applied to the
VS3± feedback point. This signal causes the unit to increase its
output voltage and, in turn, its current contribution to the load.
Digital Share Bus
The digital share bus scheme is similar in principle to the tradi-
tional analog share bus scheme. The difference is that instead of
using a voltage on the share bus to represent current, a digital
word is used.
The ADP1046A outputs a digital word onto the share bus. The
digital word is a function of the current that the power supply is
providing (the higher the current, the larger the digital word).
The power supply with the highest current controls the bus
(master). A power supply that is putting out less current (slave)
sees that another supply is providing more power to the load
than it is.
CURRENT
ADP1046A
During the next cycle, the slave increases its current output contri-
bution by increasing its output voltage. This cycle continues until
the slave outputs the same current as the master, within a pro-
grammable tolerance range. Figure 32 shows the configuration
of the digital share bus.
VDD
SHAREi
CURRENT SENSE
INFO
DIGITAL
WORD
POWER SUPPLY A
SHAREo
SHAREi
SHARE
BUS
CURRENT SENSE
INFO
DIGITAL
WORD
SHAREo
POWER SUPPLY B
Figure 32. Digital Current Share Configuration
The digital share bus is based on a single-wire communication
bus principle; that is, the clock and data signals are contained
together.
When two or more ADP1046A devices are connected, they syn-
chronize their share bus timing. This synchronization is performed
by the start bit at the beginning of a communications frame. If a
new ADP1046A is hot-swapped onto an existing digital share
bus, the device waits to begin sharing until the next frame. The
new ADP1046A monitors the share bus until it sees a stop bit,
which designates the end of a share frame. It then performs
synchronization with the other ADP1046A devices during the
next start bit. The digital share bus frame is shown in Figure 34.
CS2+
CS2–
CURRENT
SENSE
ADC
BIT STREAM
SHARE
BUS
SHAREo
BIT STREAM
VOLTAGE
LPF
Figure 33. Analog Current Share Configuration
2 STOP BITS START BIT
(IDLE)
0
8-BIT DATA
2 STOP BITS START BIT
(IDLE)
0
PREVIOUS
FRAME
FRAME
Figure 34. Digital Current Share Frame Timing Diagram
NEXT FRAME
Rev. 0 | Page 25 of 88
 

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