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ADP1046ACPZ-R7 View Datasheet(PDF) - Analog Devices

Part Name
Description
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ADP1046ACPZ-R7 Datasheet PDF : 96 Pages
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ADP1046
Parameter
Measurement Accuracy
Temperature Readings
According to Internal
Linearization Scheme
OTP
Threshold Accuracy
Comparator Speed
OTP Threshold Hysteresis
PGOOD1, PGOOD2, SHAREo PINS
(OPEN DRAIN)
Output Low Voltage
PSON, FLAGIN, SHAREi PINS
(DIGITAL INPUTS)
Input Low Voltage
Input High Voltage
FLAGIN Propagation Delay
Leakage Current
GATE PIN
Output Low Voltage
Output High Voltage
SDA/SCL PINS
Input Low Voltage
Input High Voltage
Output Low Voltage
Leakage Current
SERIAL BUS TIMING
Clock Operating Frequency
Bus-Free Time
Start Hold Time
Start Setup Time
Stop Setup Time
SDA Setup Time
SDA Hold Time
SCL Low Timeout
SCL Low Period
SCL High Period
Clock Low Extend Time
SCL, SDA Fall Time
SCL, SDA Rise Time
Symbol Test Conditions/Comments
Min
Typ
Factory trimmed at 1 V
0 mV to 160 mV
−0.5
−8
0% to 100% of usable input voltage range −3.0
−42
RTD source set to 46 μA (Register 0x11 set to
0xE6); NTC R0 = 100 kΩ, 1%, beta = 4250, 1%;
REXT = 16.5 kΩ, 1%
25°C to 100°C
100°C to 125°C
T = 85°C with 100 kΩ||16.5 kΩ
T = 100°C with 100 kΩ||16.5 kΩ
−0.9
−14.4
−0.5
−8
10.5
16
VOL
VIL
VIH
VDD − 0.4
Does not include debounce time (Register
200
0x0A[3] = 1); flag action set to disable PSU
VOL
VOH
VDD = 3.3 V
VIL
VIH
VOL
VDD − 0.4
VDD − 0.4
See Figure 3
10
100
tBUF
Between stop and start conditions
1.3
tHD;STA
Hold time after (repeated) start condition; 0.6
after this period, the first clock is generated
tSU;STA
Repeated start condition setup time
0.6
tSU;STO
0.6
tSU;DAT
100
tHD;DAT
For readback
125
For write
300
tTIMEOUT
25
tLOW
1.3
tHIGH
0.6
tLO;SEXT
tF
20
tR
20
Data Sheet
Max
Unit
+0.5
% FSR
+8
mV
+3.0
% FSR
+42
mV
7
5
+0.25
+4
+1.1
+17.6
°C
°C
% FSR
mV
% FSR
mV
ms
mV
0.4
V
0.4
V
V
ns
1.0
μA
0.4
V
V
0.4
V
V
0.4
V
1.0
μA
400
kHz
μs
μs
μs
μs
ns
ns
ns
35
ms
μs
μs
25
ms
300
ns
300
ns
Rev. 0 | Page 8 of 96
 

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