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ADP1043A View Datasheet(PDF) - Analog Devices

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ADP1043A Datasheet PDF : 72 Pages
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ADP1043A
PWM AND SYNCHRONOUS RECTIFIER TIMING REGISTERS
Figure 36 and Table 58 to Table 88 describe the implementation and programming of the seven PWM signals that are output from the
ADP1043A. In general, it is recommended that t1 be set to 0 and that t1 be set as the reference point for the other signals.
t2
PWM1 (OUTA)
t1
PWM2 (OUTB)
t4
t3
PWM3 (OUTC)
PWM4 (OUTD)
t5
t6
t8
t7
SYNC RECT 1 (SR1)
t10
t9
SYNC RECT 2 (SR2)
t12
t11
PWM5 (OUTAUX)
t13
t14
tPERIOD
tPERIOD
Figure 36. PWM Timing Diagram
Table 58. Register 0x3F—OUTAUX Switching Frequency Setting
Bits
Name
R/W Description
[7:6]
Reserved
R/W Reserved.
[5:0]
Switching frequency R/W This register sets the switching frequency of the OUTAUX signal.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
1
1
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
0
0
1
0
1
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
1
0
0
0
1
1
1
1
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
1
0
0
1
0
0
1
1
0
1
0
1
0
0
Frequency (kHz)
48.8
50.4
52.0
53.8
55.8
57.9
60.1
62.5
65.1
67.9
71.0
74.4
78.1
82.2
86.8
91.9
97.6
100.8
104.1
107.7
111.6
Rev. 0 | Page 50 of 72
 

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