ADP1043AACPZ-RL View Datasheet(PDF) - Analog Devices
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Description
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ADP1043AACPZ-RL Datasheet PDF : 72 Pages
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ADP1043A
Bits Name
[1:0] OVP sampling
R/W Description
R/W The OVP flag is set if the average voltage during the OVP sampling period is greater than the OVP
threshold. This OVP flag sampling period is 80 μs. The number of samples can be increased using
these bits. If the number of samples is increased, the average voltage must be greater than the
OVP threshold for each of those cycles. For example, if this value is set to two cycles, the average
voltage must be greater than the OVP threshold for both cycles.
Bit 1
Bit 0
Additional Sampling (μs)
0
0
0 (one sample sets the OVP flag)
0
1
80 (two samples set the OVP flag)
1
0
160 (three samples set the OVP flag)
1
1
240 (four samples set the OVP flag)
Table 47. Register 0x33—VS2 and VS3 Overvoltage Limit (OVP)
Bits Name
R/W Description
[7:3] VS2 and VS3
OVP setting
R/W Load overvoltage limit. This limit is programmable from 107.7% to 145.3% of the nominal VS2 or
VS3 voltage; 0x00 corresponds to 107.7%. Each LSB results in an increase of 1.21%. The VS2/VS3
OVP threshold is calculated as follows:
VSx_OVP_Threshold = [(89 + VSx_OVP_Setting)/128] × 1.55 V
For example, if the VS3 OVP setting is 10, then
VS3_OVP_Threshold = [(89 + 10)/128] × 1.55 V = 1.2 V
Setting these bits to 0 gives an OVP limit of 107.7% of the nominal VS2/VS3 voltage.
Setting these bits to 10 gives an OVP limit of 120% of the nominal VS2/VS3 voltage.
Setting these bits to 20 gives an OVP limit of 132% of the nominal VS2/VS3 voltage.
Setting these bits to 31 gives an OVP limit of 145.3% of the nominal VS2/VS3 voltage.
2
Regulating point R/W When this bit is set, the ADP1043A regulates from the VS3 node at all times. When this bit is not set,
the ADP1043A uses the VS1 voltage as the regulating point during soft start and when the OrFET is
disabled.
[1:0] OVP sampling
R/W The OVP flag is set if the average voltage during the OVP sampling period is greater than the OVP
threshold. This OVP flag sampling period is 80 μs. The number of samples can be increased using
these bits. If the number of samples is increased, the average voltage must be greater than the OVP
threshold for each of those cycles. For example, if this value is set to two cycles, the average
voltage must be greater than the OVP threshold for both cycles.
Bit 1
Bit 0
Additional Sampling (μs)
0
0
0 (one sample sets the OVP flag)
0
1
80 (two samples set the OVP flag)
1
0
160 (three samples set the OVP flag)
1
1
240 (four samples set the OVP flag)
Table 48. Register 0x34—VS1 Undervoltage Limit (UVP)
Bits Name
R/W Description
7
End of cycle
shutdown
R/W This bit is valid only when the OUTAUX pin is used for regulation. When any flag shuts down the
power supply, the OUTAUX PWM is immediately shut down. This bit specifies when the other PWM
outputs are shut down.
1: All other PWM outputs are shut down at the end of the switching cycle.
0: All other PWM outputs are immediately shut down.
[6:0] VS1 UVP setting
R/W These bits set the UVP limit to one of 128 settings. The UVP limit can be programmed from 0% to
155% of the nominal VS1 voltage. Each LSB increases the voltage by 155%/128 = 1.21%. In reality,
there are 82 usable settings, which program the UVP threshold from 0% to 100% of the nominal
VS1 voltage. The VS1 UVP threshold is calculated as follows:
VS1_UVP_Threshold = [(VS1_UVP_Setting)/128] × 1.55 V
For example, if the VS1 UVP setting is 60, then
VS1_UVP_Threshold = [60/128] × 1.55 V = 726 mV
Setting these bits to 0 gives a UVP limit of 0% of the nominal VS1 voltage.
Setting these bits to 66 (0x42) gives a UVP limit of 80% of the nominal VS1 voltage.
Setting these bits to 82 (0x52) gives a UVP limit of 100% of the nominal VS1 voltage.
Setting these bits to 127 (0x7F) gives a UVP limit of 155% of the nominal VS1 voltage.
Rev. 0 | Page 47 of 72
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