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ADP1043AACPZ-RL View Datasheet(PDF) - Analog Devices

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ADP1043AACPZ-RL Datasheet PDF : 72 Pages
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ADP1043A
Table 36. Register 0x28—Volt-Second Balance Gain Setting
Bits
Name
R/W Description
[7:2]
Reserved
R/W Reserved.
[1:0]
VS balance gain
setting
R/W These bits set the gain of the volt-second balance circuit. The gain can be changed by a factor of
64. When these bits are set to 00, it takes approximately 700 ms to achieve volt-second balance.
When these bits are set to 11, it takes approximately 10 ms to achieve volt-second balance.
Bit 1
Bit 0
Volt-Second Balance Gain
0
0
1
0
1
4
1
0
16
1
1
64
Table 37. Register 0x29—Share Bus Bandwidth
Bits
Name
R/W Description
[7:5]
Reserved
R/W Reserved.
4
Bit stream
R/W 1 = the current sense ADC reading is output on the SHAREo pin. This bit stream can be used for
analog current sharing.
0 = the digital share bus signal is output on the SHAREo pin. This signal can be used for digital
current sharing.
3
Current share select R/W 1 = CS1 reading used for current share.
0 = CS2 reading used for current share.
[2:0]
Share bus bandwidth R/W These bits determine the amount of bandwidth dedicated to the share bus. The value 000 is
the lowest possible bandwidth, and the value 111 is the highest possible bandwidth.
Table 38. Register 0x2A—Share Bus Setting
Bits
Name
R/W Description
[7:4]
Number of bits
R/W These bits determine how much a master device reduces its output voltage to maintain
dropped by master
current sharing.
[3:0]
Bit difference between R/W These bits determine how closely a slave tries to match the current of the master device. The
master and slave
higher the setting, the larger the distance that satisfies the current sharing criteria.
Table 39. Register 0x2B—Temperature Gain Trim
Bits
Name
R/W Description
[7:5]
Reserved
R/W Set these bits to 000 for normal operation.
4
Gain polarity
R/W 1 = negative gain is introduced.
0 = positive gain is introduced.
[3:0]
Gain trim
R/W This register calibrates the RTD ADC gain. It calibrates for errors in the ADC. This value allows
±12% trim to be realized.
Rev. 0 | Page 43 of 72
 

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