ADP1043AACPZ-RL View Datasheet(PDF) - Analog Devices
Part Name
Description
View to exact match
ADP1043AACPZ-RL Datasheet PDF : 72 Pages
| |||
ADP1043A
DETAILED REGISTER DESCRIPTIONS
FAULT REGISTERS
Register 0x04 to Register 0x07 are latched fault registers. In these registers, flags are not reset when the fault disappears. Flags are cleared
only by a register read (provided that the fault no longer persists). Note that latched bits are clocked on a low-to-high transition only. Also
note that these register bits are cleared when read via the I2C interface unless the fault is still present. It is recommended that the latched
fault register be read again after the faults disappear to ensure that the register is reset.
Table 8. Register 0x00—Fault Register 1 and Register 0x04—Latched Fault Register 1 (1 = Fault, 0 = Normal Operation)
Bits Name
R/W Description
Register
Action
7
Power supply
R
1 = power supply is off. All PWM outputs are disabled. This bit
stays high until the power supply is restarted.
None
6
OrFET
R
1 = OrFET control signal at the GATE pin (Pin 16) is off.
0x30
5
PGOOD1 fault R
1 = Power-Good 1 fault. At least one of the following flags has been
set: power supply, CS1 fast OCP, CS1 accurate OCP, CS2 accurate
OCP, UVP, local OVP, or load OVP.
None
4
PGOOD2 fault R
1 = Power-Good 2 fault. At least one of the following flags has
been set: power supply, OrFET, CS1 fast OCP, CS1 accurate OCP,
CS2 accurate OCP, voltage continuity, UVP, accurate OrFET disable,
ACSNS, external flag (FLAGIN), VCORE OV, VDD OV, local OVP, load
OVP, OTP, CRC fault, and EEPROM unlocked. (The user can choose to
ignore one or more flags. See Table 41 for more information.)
0x2D
None
3
SR off
R
Sync rects are disabled. This flag is set when one of the following
None
cases is true:
SR1 and SR2 are disabled by the user.
0x5D
The load current has fallen below the threshold in Register 0x3B. 0x3B
A flag that was configured to disable the sync rects has been set. 0x08 to 0x0D
2
CS1 fast OCP
R
CS1 current is above its fast overcurrent protection limit. This is a
1.2 V threshold on the CS1 pin. Fast OCP is a comparator.
Programmable
1
CS1 accurate OCP R
CS1 current is above its accurate overcurrent protection limit.
0x22
Programmable
0
CS2 accurate OCP R
CS2 current is above its accurate overcurrent protection limit.
0x26
Programmable
Table 9. Register 0x01—Fault Register 2 and Register 0x05—Latched Fault Register 2 (1 = Fault, 0 = Normal Operation)
Bits Name
R/W Description
Register Action
7
Voltage
continuity
R
Voltage differential between VS1 and VS2 pins or between VS2
and VS3 pins is outside limits. Either (VS1 − VS2) > 100 mV or
(VS2 − VS3) > 100 mV.
Programmable
6
UVP
R
VS1 is below its undervoltage limit.
0x34
Programmable
5
Accurate OrFET R
disable
Reverse voltage across CS2 pins is above limit. This is the accurate 0x30
OrFET reverse voltage.
Programmable
4
VDD UV
R
VDD is below limit.
Immediate shutdown
3
VCORE OV
R
2.5 V VCORE is above limit.
Immediate shutdown
2
VDD OV
R
VDD is above limit. The I2C interface stays functional, but a PSON 0x0E
Programmable
toggle is required to restart the power supply.
1
Load OVP
R
VS2 or VS3 is above its overvoltage limit.
0x33
Programmable
0
Local OVP
R
VS1 is above its overvoltage limit.
0x32
Programmable
Table 10. Register 0x02—Fault Register 3 and Register 0x06—Latched Fault Register 3 (1 = Fault, 0 = Normal Operation)
Bits Name
R/W Description
Register Action
7
OTP
R
6
Reserved
R
5
Share bus
R
4
Constant current R
3
Reserved
R
2
Line impedance R
1
Soft start filter R
0
External flag
R
Temperature is above OTP limit.
Reserved.
Current share is outside regulation limit.
Power supply is operating in constant current mode (constant
current mode is enabled).
Reserved.
Line impedance between VS2 and VS3 is above limit.
The soft start filter is in use.
The external flag pin (FLAGIN) is set.
0x2F
0x2A
0x27
0x35
0x5F
Programmable
Programmable
None
None
None
Programmable
Rev. 0 | Page 35 of 72
|
|
Share Link: 