ADP1043A View Datasheet(PDF) - Analog Devices

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ADP1043A

Digital Controller for Isolated Power Supply Applications

Analog Devices 

SOFT START

A dedicated filter is used during soft start. The filter is disabled

at the end of the soft start routine, and the voltage loop digital

filter is used.

Fault Condition During Soft Start

If a CS1 fast OCP fault condition occurs during soft start, the

entire soft start routine is reset, and the ADP1043A begins another

soft start routine. All other fault flags are ignored during soft start.

Soft Start Routine

When the user turns on the power supply (enables PSON), the

following soft start procedure occurs:

1. The PSON signal is enabled at Time t0. The ADP1043A

checks that initial flags are OK. These flags include VDD

OK and GND OK.

2. The ADP1043A waits for Time t1 before it begins soft start.

The length of t1 is set in Register 0x2C, Bits[4:3].

t0

t1

PSON

ADP1043A

3. The soft start begins to ramp up the power supply voltage

at the start of Time t2.

4. The ADP1043A keeps the OrFET gate signal turned off.

The voltage differential across the OrFET increases (VS1 −

VS2) due to the diode conduction of the OrFET. When the

voltage differential reaches the OrFET enable threshold

(Register 0x30, Bits[5:4]), the OrFET gate signal is enabled

at Time t3. The ADP1043A begins to regulate voltage from

VS3 instead of VS1.

5. After the power supply voltage increases above the VS1 UVP

undervoltage limit (Register 0x34, Bits[6:0]), at the end of

Time t4, the UVP flag is reset.

6. After the UVP flag is reset and if all other PGOOD1 fault

conditions are OK, the PGOOD1 signal waits for Time t5

before it is enabled. The length of t5 is programmable in

Register 0x2D, Bits[7:4].

t3

t2

t4

t5

SOFT START RAMP

VOUT VOLTAGE

(VS1 – VS2) VOLTAGE

GATE SIGNAL

LOOP CONTROLLED FROM VS1

LOOP CONTROLLED FROM VS3

UVP FLAG

PGOOD1

120mV

UVP

Figure 21. Soft Start Timing Diagram

Rev. 0 | Page 19 of 72

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