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ADP1053ACPZ-R7 View Datasheet(PDF) - Analog Devices

Part Name
Description
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ADP1053ACPZ-R7
ADI
Analog Devices ADI
ADP1053ACPZ-R7 Datasheet PDF : 84 Pages
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Data Sheet
ADP1053
CHANNEL A AND CHANNEL B DUTY CYCLE
READINGS
The Channel A and Channel B duty cycle value registers
(Register 0xFEDA and Register 0xFEDB, respectively) are up-
dated every 10 ms. The duty cycle for Channel A and Channel B
is calculated using the rising and falling edge timings of OUT1,
OUT2, OUT5, or OUT6, depending on which PWM output is
assigned to the corresponding channel. If more than one of these
PWM outputs is assigned to a channel, the PWM output used
in the duty cycle calculation is selected in the following order:
OUT1, OUT2, OUT5, OUT6.
FLAGS
The ADP1053 has an extensive set of flags (Register 0xFEC0 to
Register 0xFECB) that are set when certain limits, conditions,
and thresholds are reached. These flags include
Housekeeping flags, such as VDD_OV, EEPROM_CRC,
and EEPROM_UNLOCKED.
Flags that can be programmed for protection responses, such
as OVP_A, OVP_B, UVP_A, UVP_B, ACSNS, CS_OCP,
CS1_A_OCP, CS1_B_OCP, CS2_A_OCP, CS2_B_OCP,
OTP1, OTP2, FLAGIN, REVERSE_A, and REVERSE_B.
Status flags, such as PGOOD_A, PGOOD_B, POWER_
SUPPLY_A, POWER_SUPPLY_B, POWER_SUPPLY_C,
MODULATION_A, MODULATION_B, SOFTSTART_
FILTER_A, SOFTSTART_FILTER_B, VS_SET_ERR_A,
VS_SET_ERR_B, LIGHTLOAD_A, LIGHTLOAD_B,
FLAGOUT, OTW1, and OTW2.
For detailed descriptions of the flags, see the Flag Registers section.
The debounce time of some flags is programmable (see Table 9).
The debounce time is the time during which the fault condition
must be continuously triggered before the flag is set. Refer to
the corresponding register settings for details.
Table 9. Debounce Time of Flags
Flags
Debounce Time
VDD_OV
2 μs or 500 μs
OVP_A, OVP_B
0 μs, 0.96 μs, 2.24 μs, or 8 μs
UVP_A, UVP_B
0 ms or 100 ms
ACSNS
0 ms, 2.6 ms, 10.4 ms, or 100 ms
CS_OCP, CS1_A_OCP,
CS1_B_OCP
0 ns, 40 ns, 80 ns, or 120 ns
CS2_A_OCP, CS2_B_OCP
0 ms, 20 ms, 200 ms, or 1 sec
OTP1, OTP2
100 ms
OTW1, OTW2
0 ms or 100 ms
FLAGIN
0 μs or 100 μs
REVERSE_A, REVERSE_B
40 ns or 200 ns
The debounce time is for flag setting. There is no debounce time
for flag clearing, which means that when the flag condition no
longer exists, the flag is cleared immediately. However, the reenable
delay time functions as the debounce time for flag clearing. For
more information, see the Protection Actions section.
HOUSEKEEPING FLAGS
The VDD_OV flag (Bit 6 of Register 0xFEC2) is set when the
VDD voltage is higher than the 3.9 V OVLO threshold. The
debounce time can be set to 2 μs or 500 μs using Bit 4 of
Register 0xFE06. When the VDD_OV flag is set, the ADP1053
shuts down. If Bit 5 of Register 0xFE06 is set, the flag is always
cleared regardless of the VDD voltage.
The EEPROM_CRC flag (Bit 1 of Register 0xFEC2) indicates
that an error has occurred when downloading the EEPROM
contents to the internal registers. The part shuts down and
requires a PSON_A/PSON_B reset to restart.
The EEPROM_UNLOCKED flag (Bit 4 in Register 0xFEC3)
indicates that the EEPROM is in the unlocked state and can
be updated.
OVERVOLTAGE PROTECTION (OVP) FLAGS
The ADP1053 has two OVP analog comparators for Channel A
and Channel B, as shown in Figure 11. The OVP threshold for each
channel can be programmed from 0.75 V to 1.5 V using Register
0xFE26 for Channel A and Register 0xFE27 for Channel B.
The OVP_A and OVP_B flags (Bit 2 in Register 0xFEC0 and
Register 0xFEC1, respectively) are set when the sensed voltage
between the OVP_A and PGND_A pins (or between the OVP_B
and PGND_B pins) exceeds the programmed threshold. The
debounce time of the flag can be set to 0 μs, 1 μs, 2 μs, or 8 μs
using Register 0xFE26 and Register 0xFE27. There is also a 40 ns
propagation delay, which is measured from when the OVP_A
or OVP_B voltage exceeds the threshold to when the comparator
output status is changed.
The response to the OVP_A and OVP_B flags can be programmed
using Register 0xFE02. For more information, see the Protection
Actions section and the Flag Configuration Registers section.
UNDERVOLTAGE PROTECTION (UVP) FLAGS
The UVP_A and UVP_B flags (Bit 3 in Register 0xFEC0 and
Register 0xFEC1, respectively) are set when the voltage reading
at VS_A and VS_B goes below the UVLO threshold (program-
mable in Register 0xFE28 and Register 0xFE29). The UVP circuits
compare Bits[6:0] with the seven MSBs of the VS_A/VS_B value
registers, which means that each LSB of the UVP threshold
corresponds to 1.6 V × 32/4096 = 12.5 mV.
For example, with an 11 kΩ/1 kΩ divider and with Bits[6:0] of
Register 0xFE28 = 0x30 (48 decimal), the UVP_A threshold is
12.5 mV × 48 × 12 = 7.2 V
Note that UVP is ignored when its threshold value is set to 0.
The debounce time of the flag can be set to 0 ms or 100 ms
using Bit 7 of Register 0xFE28 and Register 0xFE29. Because the
VS_A/VS_B reading is the average value over every 10 ms, there
is an additional debounce and delay time of up to 10 ms.
Rev. A | Page 27 of 84
 

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