Data Sheet
Example
In a fixed duty cycle, full-bridge application, OUT1 through
OUT 4 are assigned to Channel C with soft start enabled. The
switching frequency is 104.2 kHz, the switching cycle is 9.6 μs,
tR1 = 0 μs, tF1 = 4 μs, tR2 = 4.8 μs, tF2 = 8.8 μs, tR3 = 4.2 μs, tF3 =
9.4 μs, tR4 = 9 μs, and tF4 = 4.6 μs. Therefore, tSS_C1 = tSS_C2 = 4 μs.
For soft start, the falling edges of OUT1 and OUT2 are
configured for negative modulation, and the rising edges of
OUT3 and OUT4 are configured for negative modulation.
Given this setup, soft start for Channel C operates as follows:
• OUT1: The rising edge is fixed. At the beginning of soft
start, the falling edge is located at tF1 − tSS_C1 = 0, which
means a zero duty cycle. The edge moves to the right
during soft start and stops at the tF1 value of 4 μs.
• OUT2: The rising edge is fixed. At the beginning of soft
start, the falling edge is located at tF2 − tSS_C2 = 4.8 μs, which
means a zero duty cycle. The edge moves to the right
during soft start and stops at the tF2 value of 8.8 μs.
• OUT3: The falling edge is fixed. At the beginning of soft
start, the rising edge is located at tR3 − tSS_C1 = 0.2 μs. The
edge moves to the right during soft start and stops at the
tR3 value of 4.2 μs.
• OUT4: The falling edge is fixed. At the beginning of soft
start, the rising edge is located at tR4 − tSS_C2 = 5 μs. The
edge moves to the right during soft start and stops at the
tR4 value of 9 μs.
To implement soft start for Channel C using a different PWM
timing configuration, the user can configure additional bit
settings in Register 0xFE68.
• When Bit 3 is set, tSS_C1 is forced to follow tSS_C2.
• When Bit 2 is set, tSS_C2 = |tS − tR2|, where tS is the switching
cycle for Channel C.
• When Bit 1 is set, tSS_C1 = |tF3 − tR3|.
• When Bit 0 is set, tSS_C2 = |tF4 − tR4|.
Bits[7:6] of Register 0xFE68 are used to prevent the unintentional
overlap of the PWM outputs, especially when synchronization
is enabled.
When Bit 7 is set, the falling edges of OUT1, OUT2, OUT5,
and OUT6 are always after the rising edges in one cycle during
soft start.
Bit 6 is valid only when Bit 7 of Register 0xFE68 is set to 1. If
Bit 6 is set to 0, the rising edges of OUT3, OUT4, OUT7, and
OUT8 are always after the falling edges in one cycle during soft
start. If Bit 6 is set to 1, the falling edges of OUT3, OUT4, OUT7,
and OUT8 are always after the rising edges in one cycle during
soft start.
ADP1053
Flag Timing During Soft Start
The user can program which flags are active during the soft
start. All flags are active at the end of the soft start. For more
information, see the Flag Blanking During Soft Start section.
For either regulated channel of the ADP1053, the following
procedure occurs after the user turns on the power supply
(enables PSON_A or PSON_B). See Figure 22.
1. The PSON signal is enabled at t = t0. The ADP1053 checks
that initial flags are OK.
2. The ADP1053 waits for the tDON time before it begins to
ramp up the power stage reference voltage at t1.
3. When the output voltage reaches a steady state, the soft
start is completed, and the SOFTSTART_FILTER_A or
SOFTSTART_FILTER_B flag is cleared.
4. The PGOOD signal waits for the tDGOOD time before it is
enabled at t3.
The values for tDON_A, tDON_B, tDGOOD_A, and tDGOOD_B are all
programmable.
PSON
VOUT
SOFTSTART_
FILTER
FLAG
POWER_
SUPPLY
FLAG
PGOOD
tDON
tDGOOD
t0
t1
t2
t3
Figure 22. Soft Start Timing Diagram
The restart delay time can be programmed using Register 0xFE88.
For example, in the case of a short circuit, the ADP1053 restarts
in a soft start sequence every restart delay time. This restart feature,
also called “hiccup mode,” helps to minimize power dissipation
in the event of a short circuit. For more information, see the
Protection Actions section.
The SR PWM outputs and the current balance function can be
disabled during soft start. For more information, see the PWM
Outputs (OUT1 to OUT8) section and the Synchronous Rectifier
(SR) Soft Start section.
Flag Timing During Shutdown
When a fault condition occurs, the following flags are set:
• The PGOOD_A or PGOOD_B fault flag is set.
• Depending on the fault and how it is configured, the
POWER_SUPPLY_A or POWER_SUPPLY_B flag is
enabled after a programmed time.
Rev. A | Page 23 of 84