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ADM1026 View Datasheet(PDF) - ON Semiconductor

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ADM1026 Datasheet PDF : 55 Pages
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ADM1026
Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1, 2, and 3))
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
SERIAL BUS TIMING
Start Hold Time, tHD; STA
4.0
ms
SCL Low Time, tLOW
4.7
ms
SCL High Time, tHIGH
4.0
ms
SCL, SDA Rise Time, tr
1000
ns
SCL, SDA Fall Time, tf
300
ns
Data Setup Time, tSU; DAT
250
ns
Data Hold Time, tHD; DAT
300
ns
1. All voltages are measured with respect to GND, unless otherwise specified.
2. Typicals are at TA = 25C and represent the most likely parametric norm. Shutdown current typ is measured with VCC = 3.3 V.
3. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge.
4. Total unadjusted error (TUE) includes offset, gain, and linearity errors of the ADC, multiplexer, and on-chip input attenuators. VBAT is accurate
only for VBAT voltages greater than 1.5 V (see Figure 14).
5. Total analog monitoring cycle time is nominally 273 ms, made up of 18 ms 11.38 ms measurements on analog input and internal
temperature channels, and 2 ms 34.13 ms measurements on external temperature channels.
6. The total fan count is based on two pulses per revolution of the fan tachometer output. The total fan monitoring time depends on the number
of fans connected and the fan speed. See the Fan Speed Measurement section for more details.
7. ADD is a three-state input that may be pulled high, low, or left open circuit.
8. Logic inputs accept input high voltages up to 5.0 V even when device is operating at supply voltages below 5.0 V.
9. Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117, and measured at 40C, +25C, and +85C. Typical endurance
at +25C is 700,000 cycles.
10. Retention lifetime equivalent at junction temperature (TJ ) = 55C as per JEDEC Std. 22 method A117. Retention lifetime based on activation
energy of 0.6 V derates with junction temperature as shown in Figure 15.
SCL
SDA
tBUF
P
S
t LOW
tR
tHD; STA
tHD; DAT
tF
tHIGH
tSU; DAT
t HD; STA
tSU; STA
S
Figure 2. Serial Bus Timing Diagram
tSU; STO
P
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