ADM1025ARQZ-REEL View Datasheet(PDF) - ON Semiconductor
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ADM1025ARQZ-REEL Datasheet PDF : 21 Pages
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ADM1025/ADM1025A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Preliminary Technical Data
Figure 3.Pin Configuration
Table 3. Pin Function Descriptions
Pin
No. Mnemonic
Description
1 SDA
Digital I/O. Serial bus bidirectional data. Open-drain output.
2 SCL
Digital Input. Serial bus clock.
3 GND
System Ground
4
VCC
Power. Can be powered by 3.3 V standby power if monitoring in low power states is required. This pin also
serves as the analog input to monitor VCC.
5 VID0
Digital Input. Core voltage ID readouts from the processor. This value is read into the VID0−VID3 Status
Register. It has an on-chip 100 kΩ pull-up resistor (ADM1025 only).
6 VID1
Digital Input. Core voltage ID readouts from the processor. This value is read into the VID0−VID3 Status
Register. It has an on-chip 100 kΩ pull-up resistor (ADM1025 only).
7 VID2
Digital Input. Core voltage ID readouts from the processor. This value is read into the VID0−VID3 Status
Register. It has an on-chip 100 kΩ pull-up resistor (ADM1025 only).
8 VID3
Digital Input. Core voltage ID readouts from the processor. This value is read into the VID0−VID3 Status
Register. It has an on-chip 100 kΩ pull-up resistor (ADM1025 only).
9 D−/NTI
Analog/Digital Input. Connected to cathode of external temperature sensing diode. If held high at power-up, it
initiates NAND tree test mode.
10 D+
Analog Input. Connected to anode of external temperature sensing diode.
11 12VIN/VID4
Programmable Analog/Digital Input. Defaults to 12 VIN analog input at power-up but may be pro-grammed as
VID4 Core Voltage ID readout from the processor. This value is read into the VID4 Status Register. In analog 12
VIN mode, it has an on-chip voltage attenuator. In VID4 mode, it has an on-chip 300 kΩ pull-up resistor.
12 5VIN
Analog Input. Monitors 5 V supply.
13 3.3VIN
Analog Input. Monitors 3.3 V supply.
14 2.5VIN
Analog Input. Monitors 2.5 V supply.
15
VCCPIN
Analog Input. Monitors processor core voltage (0 V to 3.0 V).
16 ADD/RST/INT/NTO Programmable Digital I/O. The lowest order programmable bit of the SMBus Address, sampled on SMB activity
as a three-state input. Can also be configured to give a minimum 20 ms low reset output pulse. Alternatively, it
can be programmed as an interrupt output for temperature/voltage interrupts. Functions as the output of the
NAND tree in NAND tree test mode.
Rev. P5 | Page 6 of 21| www.onsemi.com
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