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ADM1025ARQZ View Datasheet(PDF) - ON Semiconductor

Part Name
Description
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ADM1025ARQZ
ON-Semiconductor
ON Semiconductor ON-Semiconductor
ADM1025ARQZ Datasheet PDF : 21 Pages
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ADM1025/ADM1025A
Preliminary Technical Data
Parameter
SERIAL BUS TIMING
Clock Frequency, fSCLK
Glitch Immunity, tSW
Bus Free Time, tBUF
Start Setup Time, tSU:STA
Start Hold Time, tHD:STA
Stop Condition Setup Time, tSU:STO
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Data Setup Time, tSU:DAT
Data Hold Time, tHD:DAT
Min Typ Max Unit Test Conditions/Comments
50
1.3
600
600
600
1.3
0.6
100
300
400 kHz See Figure 2
ns
See Figure 2
μs
See Figure 2
ns
See Figure 2
ns
See Figure 2
ns
See Figure 2
μs
See Figure 2
μs
See Figure 2
300 ns
See Figure 2
300 ns
See Figure 2
ns
See Figure 2
ns
See Figure 2
1 All voltages are measured with respect to GND, unless otherwise specified.
2 Typicals are at TA = 25°C and represent most likely parametric norm. Shutdown current typ is measured with VCC = 3.3 V.
3 TUE (Total Unadjusted Error) includes Offset, Gain, and Linearity errors of the ADC, multiplexer, and on-chip input attenuators, including an external series input
protection resistor value between zero and 1 kΩ.
4 Total monitoring cycle time is nominally 114.4 ms. Monitoring Cycle consists of 6 Voltage + 1 Internal Temperature + 1 External Temperature readings.
5 ADD is a three-state input that may be pulled high, low, or left open-circuit.
6 Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.2 V for a rising edge.
Rev. P5 | Page 4 of 21| www.onsemi.com
 

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